An electrical component including a substrate, a first dielectric layer on the substrate, a redistribution layer pad on the first dielectric layer, and a component interconnection element on the redistribution layer pad so that the component interconnection element fills an opening in the second dielectric layer. The opening includes at least one protrusion between the component interconnection element solder ball metallization and the redistribution layer pad.

The electronic component package body includes a substrate, an electronic component, and first pins. The substrate includes a bottom surface, a top surface, and a first side surface. The first side surface is connected between the bottom surface and the top surface. The electronic component is packaged inside the substrate. The first pins are embedded in the substrate, and penetrate from the bottom surface to the top surface. The first pins include a bottom surface and a side surface connected to the bottom surface. The bottom surface is exposed relative to the bottom surface, and at least a partial structure of the side surface is exposed relative to the first side surface. Both the bottom surface and the side surface are used for soldering with solder. Reliability of soldering the electronic component package body and a circuit board is high.

A semiconductor device according to the present embodiment includes a substrate having a first semiconductor circuit provided thereon. First pads are located on the substrate. A first insulating layer is located on an outer side of each of the first pads. Second pads are respectively bonded to the first pads. A second insulating layer is located on an outer side of each of the second pads and is bonded to the first insulating layer. The first pads each include a first conductive material, and a first insulating material located on an inner side of the first conductive material on a bonding surface of the first pads and the second pads.

A method for manufacturing a semiconductor device includes forming a thermosetting resin film on a first metal layer, forming an opening in the resin film, forming a second metal layer that covers a region from an upper surface of the first metal layer exposed from the opening of the resin film to an upper surface of the resin film, performing heat treatment at a temperature equal to or higher than a temperature at which the resin film is cured after forming the second metal layer, forming a cover film that covers the upper surface of the resin film and a side surface of the second metal layer after performing the heat treatment, and forming a solder on an upper surface of the second metal layer exposed from an opening of the cover film after forming the cover film.

A semiconductor structure includes: a substrate, a conductive pattern layer, a support layer and a re-distribution layer. The conductive pattern layer is arranged on the substrate. The support layer covers the conductive pattern layer and is provided with a via hole. The re-distribution layer is arranged on the support, and the re-distribution layer includes a test pad at least located in the via hole. The test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole.

A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

Provided is a semiconductor package including a first chip substrate including a first surface and a second surface, a through via passing through the first chip substrate, an upper passivation layer including a trench on the second surface of the first chip substrate, the trench exposing at least a portion of the second surface of the first chip substrate, an upper pad electrically connected with the through via on the trench, a second chip substrate including a third surface and a fourth surface, a lower pad electrically connected to the second chip substrate on the third surface of the second chip substrate, and a connection bump electrically connecting the upper pad with the lower pad and contacting the lower pad, wherein a width of the connection bump increases as the connection bump becomes farther away from the first surface of the first chip substrate.

A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.

A semiconductor device includes a first layer including a plurality of first pads, and a second layer including a plurality of second pads. The plurality of first pads are bonded to the plurality of second pads, respectively. At least one of the first pads or the second pads continuously surrounds an insulating portion.

The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion.