Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

A light emitting element includes: a substrate; a first emission part and a second emission part disposed on the substrate, each comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and an active layer positioned between the first semiconductor layer and the second semiconductor layer; an insulation layer covering the first emission part and the second emission part and including: a plurality of first openings that includes multiple first openings located above the first semiconductor layer of the first emission part and multiple first openings located above the first semiconductor layer of the second emission part, and a plurality of second openings that include at least one second opening located above the second semiconductor layer of the first emission part and at least one second opening located above the second semiconductor layer of the second emission part.

A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity. The plurality of solder interconnects comprises a first solder interconnect located in the first cavity of the first pillar interconnect. A planar cross section that extends through the first cavity of the first pillar interconnect may comprise an O shape. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width; and a second pillar interconnect portion comprising a second width that is different than the first width.

A light emitting display device includes a pixel circuit unit, a data distribution unit, a plurality of signal generating units, a unit light emitting diode, and a dummy opening. The pixel circuit unit is configured to generate an output current. The data distribution unit is configured to apply a data voltage to the pixel circuit unit through a data line. The plurality of signal generating units are respectively configured to apply a scan signal and a light emission control signal to the pixel circuit unit through a plurality of signal lines. The unit light emitting diode is configured to receive the output current of the pixel circuit unit and is attached to the pixel circuit unit. The dummy opening is formed in the region where the pixel circuit unit, the data distribution unit, and a plurality of signal generating units are not positioned.

A semiconductor package including a first stack; a plurality of TSVs passing through the first stack; a second stack on the first stack and including a second surface facing a first surface of the first stack; a first pad on the first stack and in contact with the TSVs; a second pad on the second stack; a bump connecting the first and second pads; a first redundancy pad on the first surface of the first stack, spaced apart from the first pad, and not in contact with the TSVs; a second redundancy pad on the second surface of the second stack and spaced apart from the second pad; and a redundancy bump connecting the first redundancy pad and the second redundancy pad, wherein the first pad and first redundancy pad are electrically connected to each other, and the second pad and second redundancy pad are electrically connected to each other.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.

A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

A method for fabricating a semiconductor product includes forming a dielectric layer over a top level metallization layer of a semiconductor process wafer. The dielectric layer is patterned using a grayscale mask process to define a contact pad opening in the dielectric layer, thereby producing a patterned dielectric layer in which the contact pad opening is aligned to a contact pad defined in the top level metallization layer. A metal layer is deposited over the patterned dielectric layer, including within the contact pad opening. A portion of the metal layer is removed by a chemical mechanical polishing (CMP) process, with a remaining portion of the metal layer having a sloped sidewall.

The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.