A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.

A heat dissipation device includes a substrate with a network of thermally-conductive vias and thermally-conductive layers. The substrate has a first surface and a second surface opposite to the first surface. A heat dissipation interface layer including a stack of a first layer made of a first thermally-conductive material and a second layer made of a second thermally-conductive material. The first material is different from the second material. A surface of the first layer is coplanar with the first surface of the substrate. At least one of the thermally-conductive vias of said network supports and is in contact with the first layer. At least one opening thoroughly crosses the stack of the first and second layers. Material of the substrate fills the opening in the first layer.

Provided is a semiconductor device free from chipping of a thin semiconductor element during transportation. The semiconductor device includes: a thin semiconductor element including a front-side electrode on the front side of the semiconductor element, and including a back-side electrode on the back side of the semiconductor element; a metallic member formed on at least one of the front-side electrode and the back-side electrode, the metallic member having a thickness equal to or greater than the thickness of the semiconductor element; and a resin member in contact with the lateral side of the metallic member and surrounding the periphery of the metallic member, with a part of the front side of the semiconductor element being exposed.

A semiconductor package includes a die comprising at least a via and a least a hot via; a ground lead, formed directly under a back side of the die, contacting with the back side of the die, and directly connected to the a least a hot via and the at least a via of the die; a buffer layer, formed on the die, configured to absorb a stress applied to the die and prevent the die from damage; and a molding portion, formed on the die buffer layer.

An image pickup apparatus includes an image pickup device configured such that a plurality of electrode pads are disposed in a row on an inclined surface; a wiring board configured such that a plurality of first bonded electrodes that are bonded to the plurality of electrode pads via first solder bumps, respectively, are disposed in a row on a first end portion, and a plurality of second bonded electrodes are disposed in a row on a second end portion; and a signal cable configured to be bonded to the plurality of second bonded electrodes via second solder bumps, respectively. The wiring board includes a first protective film which covers the first end portion, and a second protective film which covers the second end portion, and is of a thickness that is greater than a thickness of the first protective film and less than a height of the second solder bumps.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip package stacked over the substrate. The chip package structure includes first conductive bumps arranged between and in direct contact with the chip package and the substrate providing a clearance. The chip package structure includes a chip structure having a first face and an opposing second face arranged in the clearance between the chip package and the substrate and adjacent to the first conductive bumps. The chip structure contains at least one chip. The chip package structure includes a solder cap connecting the first face of the chip structure and the chip package. The chip package structure includes a second conductive bump connecting the second face of the chip structure and the substrate.

A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad.

A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a bonding electrode, and a dummy electrode. The first semiconductor substrate has a first surface and a first wiring, and contains a first semiconductor material. The second semiconductor substrate has a second surface and a second wiring, and contains a second semiconductor material, and the first surface and the second surface face each other. The bonding electrode is arranged between the first surface and the second surface, and is electrically connected to the first wiring and the second wiring. The dummy electrode is arranged between the first surface and the second surface, and is electrically insulated from at least one of the first wiring and the second wiring. The bonding electrode has a bonding bump and a first bonding pad. The dummy electrode has a dummy bump and a first dummy pad.

A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.