A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.

A package has a package body formed by stacked insulating layers and having a front surface including a mounting area, a back surface and a side surface; a plurality of hollow portions arranged so as to be adjacent to each other on the front surface of the package body; a plurality of electrode pads individually placed on respective bottom surfaces of the hollow portions; and a partition wall formed by at least one insulating layer that forms the package body and having protruding banks at its both edge sides. Surfaces of the electrode pads are located at a lower position with respect to the front surface of the package body. The hollow portions are arranged at opposite sides of the partition wall. The electrode pads are electrically connected to respective conductor layers that are formed on the back surface and/or the side surface of the package body.

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a first isolation structure on a first surface of a substrate. A second isolation structure is formed into the first surface of the substrate. Sidewalls of the first isolation structure are disposed laterally between inner sidewalls of the second isolation structure. A bond pad is formed in the substrate such that the second isolation structure continuously laterally wraps around the bond pad.

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a first isolation structure on a first surface of a substrate. A second isolation structure is formed into the first surface of the substrate. Sidewalls of the first isolation structure are disposed laterally between inner sidewalls of the second isolation structure. A bond pad is formed in the substrate such that the second isolation structure continuously laterally wraps around the bond pad.

An inorganic light emitting diode is disclosed. The inorganic light emitting diode includes a first semiconductor layer, a second semiconductor layer having a light emitting surface composed of four sides, an active layer disposed between the first semiconductor layer and the second semiconductor layer, a first electrode coupled to the first semiconductor layer, and a second electrode coupled to the second semiconductor layer, wherein the light emitting surface has a trapezoid shape in which two opposing sides are symmetric with respect to each other.

A bonded structure is disclosed. The bonded structure can include a first element that includes a first bonding layer, the first bonding layer that has a first contact pad and a routing trace. The routing trace is formed at the same level as the first contact pad. The bonded structure can include a second element that includes a second bonding layer that has a second contact pad. The first element and the second element are directly bonded such that the first contact pad and the second contact pad are directly bonded without an intervening adhesive

A memory device is disclosed. The disclosed memory device may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a column control circuit. The second wafer may include a second logic structure including a row control circuit.

A semiconductor device includes a plurality of pads connected to an external device, a memory cell array in which a plurality of memory cells are disposed, a logic circuit configured to control the memory cell array and including a plurality of input/output circuits connected to the plurality of pads, and at least one inductor circuit connected between at least one of the plurality of pads and at least one of the plurality of input/output circuits. The inductor circuit includes an inductor pattern connected between the at least one of the plurality of pads and the at least one of the plurality of input/output circuits, and a variable pattern disposed between at least portions of the inductor pattern. The variable pattern is separated from the inductor pattern, the at least one of the plurality of pads, and the at least one of the plurality of input/output circuits.

A method of preparing a substrate for substrate bonding is provided. The method comprises: forming a recess in a substrate surface of the substrate, and forming a bondable dielectric layer on the substrate surface of the substrate. The bondable dielectric layer has a bonding surface on an opposite side of the bondable dielectric layer to the substrate surface, wherein the recess and the bondable dielectric layer define a dielectric cavity having a dielectric cavity volume. A plug is formed configured to make electrical contact to the substrate in the dielectric cavity volume. The plug has a plug volume which is less than the dielectric cavity volume, wherein the plug extends from the dielectric cavity beyond the bonding surface in a direction generally normal to the bonding surface. The plug is coined by compressing the substrate between opposing planar surfaces such that a contact surface of the plug is made co-planar with the bonding surface.

Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a “U” shape in some embodiments of the disclosure. Each end of the “U” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.