An advanced through silicon via structure for is described. The device includes a substrate including integrated circuit devices. A high aspect ratio through substrate via is disposed in the substrate. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A metallic barrier layer is disposed on the sidewalls of the through substrate via. A surface portion of the metallic barrier layer has been converted to a nitride surface layer by a nitridation process. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer fills the through substrate via and has a recess in an upper portion. A second barrier layer is disposed over the recess. A second metal layer is disposed over the second barrier layer and creates a contact.

A method of manufacturing a package structure is provided. The method of manufacturing a package structure comprises receiving a first semiconductor structure and a second semiconductor structure; forming an isolation layer on each semiconductor structure; forming at least one supporting structure and at least one pad trench in the isolation layer; filling the pad trench with electrically conductive material; plariarizing the isolation layer and the electrically conductive material to form bonding pads in a bonding layer on each semiconductor structure; and bonding the semiconductor structures.

The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

A method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device which uses an apparatus for manufacturing the semiconductor device including: a chamber, a support structure provided inside the chamber, and configured to support a bonding structure that comprises a first substrate structure, a second substrate structure, and a bonding metal layer provided between the first substrate structure and the second substrate structure, and a laser device which is provided above the chamber, the semiconductor device manufacturing method comprising: irradiating a laser beam to the bonding structure using the laser device.

A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.

A semiconductor substrate has, on an Au electrode pad, an electrolessly-plated Ni film/an electrolessly-plated Pd film/an electrolessly-plated Au film or an electrolessly-plated Ni film/an electrolessly-plated Au film and a method of manufacturing the semiconductor substrate by the steps indicated in (1) to (6) below: (1) a degreasing step; (2) an etching step; (3) a pre-dipping step; (4) a Pd catalyst application step; (5) an electroless Ni plating step; (6) an electroless Pd plating step and electroless Au plating step or an electroless Au plating step.

A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays and in-die peripheral-circuit components thereof, whereas the second die comprises processing circuits and off-die peripheral-circuit components of the 3D-M arrays. The first and second dice are communicatively coupled by a plurality of inter-die connections.

A semiconductor device according to an embodiment includes a first substrate including a first insulating layer, a first conductive layer provided in the first insulating layer, a first metal layer provided in the first insulating layer, and a second metal layer provided between the first metal layer and the first conductive layer, a linear expansion coefficient of the second metal layer being higher than that of the first metal layer; and a second substrate including a second insulating layer, and a third metal layer provided in the second insulating layer, in contact with the first metal layer. The second substrate contacts with the first substrate.

An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays and in-die peripheral-circuit components thereof, whereas the second die comprises processing circuits and off-die peripheral-circuit components of the 3D-M arrays. The first and second dice are communicatively coupled by a plurality of inter-die connections.