Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.

A display device including a film substrate including first and second surfaces, the first surface being opposite to the second surface; a semiconductor chip disposed on the first surface and including an input terminal and a test terminal, which are arranged in a first direction; a first wire extending from the input terminal on the first surface along a second direction, which intersects the first direction; and a second wire including a first extended portion, which extends along the first surface, a second extended portion, which extends along the second surface, and a first via, which penetrates the film substrate and connects the first extended portion and the second extended portion, wherein the first extended portion extends from the test terminal in the second direction and is connected to the first via, and the second extended portion extends from the first via to an edge of the second surface.

A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding.

A display device including a film substrate including first and second surfaces, the first surface being opposite to the second surface; a semiconductor chip disposed on the first surface and including an input terminal and a test terminal, which are arranged in a first direction; a first wire extending from the input terminal on the first surface along a second direction, which intersects the first direction; and a second wire including a first extended portion, which extends along the first surface, a second extended portion, which extends along the second surface, and a first via, which penetrates the film substrate and connects the first extended portion and the second extended portion, wherein the first extended portion extends from the test terminal in the second direction and is connected to the first via, and the second extended portion extends from the first via to an edge of the second surface.

A display device including a film substrate including first and second surfaces, the first surface being opposite to the second surface; a semiconductor chip disposed on the first surface and including an input terminal and a test terminal, which are arranged in a first direction; a first wire extending from the input terminal on the first surface along a second direction, which intersects the first direction; and a second wire including a first extended portion, which extends along the first surface, a second extended portion, which extends along the second surface, and a first via, which penetrates the film substrate and connects the first extended portion and the second extended portion, wherein the first extended portion extends from the test terminal in the second direction and is connected to the first via, and the second extended portion extends from the first via to an edge of the second surface.

A semiconductor device includes a substrate, a plurality of solders, and a semiconductor chip. The plurality of solders are located adjacent to each other. At least one of composition and concentration of the plurality of solders is different from each other. The semiconductor chip includes a joining surface to be joined to the substrate with the plurality of solders. The joining surface of the semiconductor chip includes a plurality of joining areas in which heat generation of the semiconductor chip or a stress on an object to be joined is different from each other. The plurality of solders are disposed to correspond to the plurality of joining areas, respectively.

A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes at least two post passivation interconnect (PPI) lines over the first passivation layer, wherein a top portion of each of the at least two PPI lines has a rounded shape. The semiconductor device further includes a second passivation layer configured to stress the at least two PPI lines. The semiconductor device further includes a polymer material over the second passivation layer and filling a trench between adjacent PPI lines of the at least two PPI lines.

An electronic apparatus includes an electronic panel including a first pad part and a second pad part having a portion electrically connected to the first pad part, a driving circuit including a bump part overlapping the first pad part in a plan view, and a circuit board including a lead part overlapping the second pad part in a plan view. The lead part including a plurality of test leads includes a first test lead group electrically connected to the first pad part, and a second test lead group insulated from the first pad part, and one test lead of the first test lead group and one test lead of the second test lead group are electrically connected to each other.

A method of manufacturing a semiconductor device includes depositing a first passivation layer over a substrate, depositing a conductive material over the first passivation layer, patterning the conductive material to form a redistribution layer (RDL) structure, and depositing a second passivation layer configured to change a shape of a top portion of the RDL structure.

Provided is a bonding method for directly bonding an electrode part of a chip component to a bonding part provided on a substrate that is a bonding target, the method comprising: a step for placing the substrate on a stage inside a liquid vessel; a step for injecting liquid into the liquid vessel; and a step for bonding the electrode part of the chip component to the bonding part (electrode part) of the bonding target by superimposing the chip component held by a bonding head in the liquid stored in the liquid vessel over the bonding target and then applying pressure thereto.