A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.

A light-emitting device includes: a light-emitting element; a coating member that covers the light-emitting element; and two external connection electrodes exposed form a first surface of the coating member. Each of the external connection electrodes includes an electrode buried in the coating member; and a metal layer formed on the electrode. A surface of each of the metal layers is exposed from the first surface of the coating member. The first surface of the coating member includes a plurality of grooves between the external connection electrodes.

Present disclosure provides a semiconductor structure, including a substrate, a pad on the substrate, a conductive layer electrically coupled to the pad at one end, a metal bump including a top surface and a sidewall, a solder bump on the top surface of the metal bump, a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer, and a polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap. A method for fabricating a semiconductor device is also provided.

A semiconductor apparatus according to the present invention includes: a semiconductor component including a cell array and a plurality of wirings; and a semiconductor component including a plurality of pads connected to the semiconductor component including the cell array. A first row pad connected to a row wiring connected to a first cell and a second cell, a second row pad connected to a row wiring connected to a third cell and a fourth cell, and a column pad connected to a column wiring connected to the first cell and the third cell are arranged such that a straight line connecting the first row pad and the column pad crosses a straight line connecting the second row pad and the column pad.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.

A semiconductor structure includes an oval-shaped pad and a dielectric layer. The oval-shaped pad is on a substrate and includes a major axis corresponding to the largest distance of the oval-shaped pad. The major axis is toward a geometric center of the substrate. The dielectric layer covers the substrate and surrounds the oval-shaped pad.

An array substrate includes connecting leads, a signal channel region extending in a first direction, a first power voltage lead, and a second power voltage lead. Any one of the signal channel region includes at least two control region columns extending in the first direction, and any one of the control region columns includes a plurality of control regions arranged along the first direction. Any one of the control regions includes a pad connecting circuit and a first pad group for bonding a microchip, the first pad group is electrically connected to the first power voltage lead. The pad connection circuit includes a plurality of second pad groups, and is provided with a first end electrically connected to the first pad group, and a second end electrically connected to the second power voltage lead.

A transistor device includes a substrate and a plurality of transistor unit cells arranged in parallel on the substrate. Each of the transistor unit cells includes a source contact, a drain contact, and a gate finger between the source contact and the drain contact. The gate finger extends in a first direction and has a first end and a second end. The transistor device further includes a first solder bump on the transistor device that is within a periphery of the active region of the device and is electrically connected to the gate finger of a first one of the unit cells at a feed point that is between the first end and the second end of the gate finger.

A semiconductor device includes an insulating substrate, wiring layers, heat dissipation layers, a semiconductor element, and a sealing resin. The wiring layers each have a first obverse face and a first reverse face oriented in opposite directions in a thickness direction of the substrate. The first reverse faces of the wiring layers are connected to the substrate. The heat dissipation layers each have a second obverse face oriented in the same direction as the first obverse face, and a second reverse face oriented opposite to the second obverse face in the thickness direction. The heat dissipation layers are located opposite to the plurality of wiring layers in the thickness direction with respect to the substrate. The second obverse faces of the heat dissipation layers are connected to the substrate. The semiconductor element is connected to one of the first obverse faces of the wiring layers. The sealing resin covers the substrate, the wiring layers, and the semiconductor element. As viewed in the thickness direction, the wiring layers overlap with the heat dissipation layers, respectively.