Provided is an electronic package, including a first substrate of a first conductive structure and a second substrate of a second conductive structure, where a first conductive layer, a bump body and a metal auxiliary layer of the first conductive structure are sequentially formed on the first substrate, and a metal pillar, a second conductive layer, a metal layer and a solder layer of the second conductive structure are sequentially formed on the second substrate, such that the solder layer is combined with the bump body and the metal auxiliary layer to stack the first substrate and the second substrate. Therefore, the arrangement of the bump body and the metal auxiliary layer allows complete reaction of the IMCs after reflowing the solder layer, and the volume of the conductive structures will not continue to shrink. As such, the problem of cracking of the conductive structures can be effectively averted.

A method for electrical connection by hybridisation of a first component with a second component. The method comprises the following steps: forming pads of ductile material in contact respectively with connection zones of the first component; forming inserts of conductive material in contact with the connection zones of the second component; forming hybridisation barriers arranged between the inserts and electrically insulated from each other, the first and second hybridisation barriers serving as a barrier by containing the deformation of the pads of ductile material during the connection of the connection zones of the first component with those of the second component. The disclosure also relates to an assembly of two connected components.

A semiconductor package may include: a first semiconductor chip; a second semiconductor chip disposed over the first semiconductor chip; and a bump structure interposed between the first semiconductor chip and the second semiconductor chip to connect the first semiconductor chip and the second semiconductor chip, wherein the bump structure includes a core portion and a shell portion, the shell portion surrounding all side ails of the core portion, and wherein the shell portion has a higher melting point than the core portion.

An assembly includes at least one first element comprising at least one first electrical bonding pad; at least one second element comprising at least one second electrical bonding pad; electrical and mechanical interconnect means, wherein the electrical and mechanical interconnect means comprise at least: at least one first intermediate metal interconnect element, on the surface of at least the first electrical bonding pad; at least one sintered joint of metal microparticles or nanoparticles stacked with the first intermediate metal interconnect element; the melting point of the first intermediate metal interconnect element being greater than the sintering temperature of the metal microparticles or nanoparticles. A method for fabricating an assembly is also provided.

The present disclosure provides a driving substrate and a manufacturing method thereof, and a micro LED bonding method. The driving substrate includes: a base substrate; a driving function layer provided on the base substrate, and including a plurality of driving thin film transistors and a plurality of common electrode lines; a pad layer including a plurality of pads provided on a side of the driving function layer away from the base substrate, each pad including a pad body and a microstructure of hard conductive material provided on a side of the pad body away from the base substrate; and a plurality of buffer structures provided on the side of the driving function layer away from the base substrate, each buffer structure surrounding a portion of a corresponding microstructure close to the base substrate, and a height of the buffer structure being lower than a height of the microstructure.

A connection arrangement for forming a component carrier structure is disclosed. The connection arrangement includes a first electrically conductive connection element and a second electrically conductive connection element. The first connection element and the second connection element are configured such that, upon connecting the first connection element with the second connection element along a connection direction, a form fit is established between the first connection element and the second connection element that limits a relative motion between the first connection element and the second connection element in a plane perpendicular to the connection direction. A component carrier and a method of forming a component carrier structure are also disclosed.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a stress-relieving structure including a conductive frame positioned above the semiconductor substrate and a plurality of insulating pillars positioned within the conductive frame, and a conductive structure including a supporting portion positioned above the stress-relieving structure, a conductive portion positioned adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion. A width of the conductive frame is equal to a width of a bottom of the conductive portion.

A semiconductor device includes a first semiconductor chip including a conductive pad, an insulating layer provided on the conductive pad, and having an aperture exposing a part of the conductive pad, and a first bump layer provided on the insulating layer and connected to the conductive pad via the aperture, and a second semiconductor chip including an electrode and a second bump layer provided on the electrode. The first bump layer includes a recessed portion provided at the aperture and in contact with the second bump layer, and a raised portion provided adjacent the aperture and in contact with the second bump layer.

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.