A display device includes a drive circuit on an insulating substrate; a connecting electrode electrically connected to the drive circuit; an LED element electrically connected to the drive circuit via the connecting electrode, and a first light reflecting layer overlapping the LED element and having an inclined surface. The inclined surface reflects light incident on the inclined surface through the LED element toward the connecting electrode. The first light reflecting layer may have a reflectance of 90 percent or more for light at a wavelength of 1.0 μm or more to 1.5 μm or less.

A system includes a semiconductor substrate having a first cavity. The semiconductor substrate forms a pedestal adjacent the first cavity. A device overlays the pedestal and is bonded to the semiconductor substrate by metal within the first cavity. A plurality of second cavities are formed in a surface of the pedestal beneath the device, wherein the second cavities are smaller than the first cavity. In some of these teachings, the second cavities are voids. In some of these teachings, the metal in the first cavity comprises a eutectic mixture. The structure relates to a method of manufacturing in which a layer providing a mask to etch the first cavity is segmented to enable easy removal of the mask-providing layer from the area over the pedestal.

A package structure includes a redistribution layer having a first surface, a second surface disposed opposite to the first surface, and at least one sidewall connected to the first surface and the second surface, at least one bonding electrode disposed on the first surface of the redistribution layer, and a mounting layer disposed on the second surface of the redistribution layer. The mounting layer includes a plurality of conductive pads that are spaced apart from each other. At least one of the conductive pads is exposed by the sidewall of the redistribution layer.

A process for packaging at least one component includes the steps of: a) providing a substrate and a packaging material layer, b) forming the packaging material layer into an adhesively semi-cured packaging material layer, c) adhering the adhesively semi-cured packaging material layer to an array, d) providing a packaging unit including at least one eutectic metal bump pair, e) permitting the eutectic metal bump pair to be in contact with at least one electrode pair on the array, f) subjecting the electrode pair to eutectic bonding to the eutectic metal bump pair, g) encapsulating the component by pressing, h) completely curing the adhesively semi-cured packaging material layer, and i) removing the substrate.

A bonding structure is a bonding structure which bonds a light emitting element and a substrate and includes a first electrode formed on the light emitting element, a second electrode formed on the substrate, and a bonding layer which bonds the first electrode and the second electrode, and the bonding layer contains a first bonding metal component and a second bonding metal component different from the first bonding metal component.

A system includes a semiconductor substrate having a first cavity. The semiconductor substrate forms a pedestal adjacent the first cavity. A device overlays the pedestal and is bonded to the semiconductor substrate by metal within the first cavity. A plurality of second cavities are formed in a surface of the pedestal beneath the device, wherein the second cavities are smaller than the first cavity. In some of these teachings, the second cavities are voids. In some of these teachings, the metal in the first cavity comprises a eutectic mixture. The structure relates to a method of manufacturing in which a layer providing a mask to etch the first cavity is segmented to enable easy removal of the mask-providing layer from the area over the pedestal.

An electronic device comprises a target substrate, a micro semiconductor structure array, a conductor array, and a connection layer. The micro semiconductor structure array is disposed on the target substrate. The conductor array corresponds to the micro semiconductor structure array, and electrically connects the micro semiconductor structure array to a pattern circuit of the target substrate. The conductors of the conductor array are independent from one another. Each conductor is an integrated member formed by eutectic bonding a conductive pad of the target substrate and a conductive electrode of the corresponding one of the micro semiconductor structures of the micro semiconductor structure array. The connection layer connects the micro semiconductor structures to the target substrate. The connection layer excludes a conductive material. The connection layer contacts and surrounds the conductors, so that the connection layer and the conductors together form a one-layer structure.

A resonator including a lower electrode, an upper electrode, and a piezoelectric film that is formed between the lower electrode and the upper electrode. A MEMS device is provided that includes an upper lid that faces the upper electrode, and a lower lid that faces the lower electrode and that seals the resonator together with the upper lid. A CMOS device is mounted on a surface of the upper lid or the lower lid opposite a surface that faces the resonator. The CMOS device includes a CMOS layer and a protective layer that is disposed on a surface of the CMOS layer opposite a surface that faces the resonator. The upper or lower lid to which the CMOS device is joined includes a through-electrode that electrically connects the CMOS device to the resonator.

A chip interconnection structure, a chip and a chip interconnection method. The chip interconnection structure includes a first chip and at least one second chip, where a transfer surface of the first chip and a transfer surface of the second chip are disposed oppositely, at least one conductive component is further provided between the second chip and the first chip, each conductive component includes at least one conductive member, and the conductive member is connected between a pad of the second chip and a pad of the first chip. The chip interconnection structure can allow two or more than two chips to be interconnected and to communicate at a high speed.

A film-type semiconductor package includes a metal lead portion arranged on a film substrate, a semiconductor chip including a pad, and a bump connecting the metal lead portion to the pad of the semiconductor chip. The bump includes a metal pillar arranged on the pad and including a first metal and a soldering portion arranged on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal.