Patent classifications
H01L2224/16502
SEGMENTED PEDESTAL FOR MOUNTING DEVICE ON CHIP
A system includes a semiconductor substrate having a first cavity. The semiconductor substrate forms a pedestal adjacent the first cavity. A device overlays the pedestal and is bonded to the semiconductor substrate by metal within the first cavity. A plurality of second cavities are formed in a surface of the pedestal beneath the device, wherein the second cavities are smaller than the first cavity. In some of these teachings, the second cavities are voids. In some of these teachings, the metal in the first cavity comprises a eutectic mixture. The structure relates to a method of manufacturing in which a layer providing a mask to etch the first cavity is segmented to enable easy removal of the mask-providing layer from the area over the pedestal.
Chip Packaging Structure and Related Inner Lead Bonding Method
A chip packaging structure includes a chip and a film substrate. The chip is formed with a gold bump, and the film substrate is formed with an inner lead, wherein the gold bump includes a first bonding surface and a plurality of side walls. The gold bump is electrically connected to the inner lead through a eutectic material coverage layer, and the first bonding surface and at least one of the plurality of side walls are covered by the eutectic material coverage layer.
JUNCTION STRUCTURE
A bonding structure is a bonding structure which bonds a light emitting element and a substrate and includes a first electrode formed on the light emitting element, a second electrode formed on the substrate, and a bonding layer which bonds the first electrode and the second electrode, and the bonding layer contains a first bonding metal component and a second bonding metal component different from the first bonding metal component.
SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD OF FABRICATING SAME
A semiconductor packaging structure manufactured in a manner which does not leave the chip damaged or susceptible to damage upon the removal of temporary manufacturing supports includes at least one electrical conductor, at least one conductive layer, a chip, and a colloid. The chip is spaced from the conductive layer, the electrical conductor is disposed between the conductive layer and the chip and electrically connects the conductive layer to the chip. The colloid covers all outer surfaces of the chip. A method of fabricating such a semiconductor packaging structure is also provided.
PROCESS FOR PACKAGING COMPONENT
A process for packaging at least one component includes the steps of: a) providing a substrate and a packaging material layer, b) forming the packaging material layer into an adhesively semi-cured packaging material layer, c) adhering the adhesively semi-cured packaging material layer to an array, d) providing a packaging unit including at least one eutectic metal bump pair, e) permitting the eutectic metal bump pair to be in contact with at least one electrode pair on the array, f) subjecting the electrode pair to eutectic bonding to the eutectic metal bump pair, g) encapsulating the component by pressing, h) completely curing the adhesively semi-cured packaging material layer, and i) removing the substrate.
RESONANCE DEVICE
A resonator including a lower electrode, an upper electrode, and a piezoelectric film that is formed between the lower electrode and the upper electrode. A MEMS device is provided that includes an upper lid that faces the upper electrode, and a lower lid that faces the lower electrode and that seals the resonator together with the upper lid. A CMOS device is mounted on a surface of the upper lid or the lower lid opposite a surface that faces the resonator. The CMOS device includes a CMOS layer and a protective layer that is disposed on a surface of the CMOS layer opposite a surface that faces the resonator. The upper or lower lid to which the CMOS device is joined includes a through-electrode that electrically connects the CMOS device to the resonator.
3D integration using Al—Ge eutectic bond interconnect
A method includes aligning a germanium feature on a first CMOS wafer with an aluminum feature on a second CMOS wafer. The aluminum feature and the germanium feature are pressed together. A eutectic bond is formed connecting the aluminum feature to the germanium feature. The eutectic bond has a melting point which is lower than the melting point of aluminum and the melting point of germanium.
MULTILAYERED TRANSIENT LIQUID PHASE BONDING
A bonding structure includes a first layer of first alloy component disposed on a substrate and a first layer of a second alloy component disposed on the first alloy component. The second alloy component has a lower melting temperature than the first alloy component. A second layer of the first alloy component is disposed on the first layer of the second alloy component and a second layer of the second alloy component is disposed on the second layer of the first alloy component.
NON-PLANAR SEMICONDUCTOR DEVICE HAVING CONFORMING OHMIC CONTACTS
An apparatus includes a non-planar semiconductor body; and a contact for the semiconductor body. The contact includes an epitaxial material that is formed on and contacts the semiconductor body. The contact includes a second material that is formed on and contacts the epitaxial material; and the second material at least partially conforms to an undercut of the epitaxial material.
Multilayered transient liquid phase bonding
A bonding structure includes a first layer of first alloy component disposed on a substrate and a first layer of a second alloy component disposed on the first alloy component. The second alloy component has a lower melting temperature than the first alloy component. A second layer of the first alloy component is disposed on the first layer of the second alloy component and a second layer of the second alloy component is disposed on the second layer of the first alloy component.