A semiconductor chip that includes a chip body that has a first side surface, a second side surface, a third side surface, and a fourth side surface; a central region at a central portion of the chip body; and a peripheral region at a peripheral portion of the chip body and adjacent to at least one of the first side surface to the fourth side surface, wherein the peripheral region includes a first unit region that includes a plurality of first bumps of a first bump density, and a second unit region that includes a plurality of second bumps of a second bump density higher than the first bump density.

A semiconductor package including a package redistribution layer, a cover insulating layer on the package redistribution layer; a lower semiconductor chip arranged between the package redistribution layer and the cover insulating layer and electrically connected to the package redistribution layer, a lower molding layer surrounding the lower semiconductor chip and filling between the package redistribution layer and the cover insulating layer, a plurality of connection posts electrically connected to the package redistribution layer by passing through the cover insulating layer and the lower molding layer, an upper semiconductor chip arranged above the cover insulating layer electrically connected to the plurality of connection posts, and an upper molding layer filling between the upper semiconductor chip and the cover insulating layer and surrounding the upper semiconductor chip may be provided.