A method of forming an inductor including forming a first redistribution structure on a substrate, forming a first conductive via over and electrically connected to the first redistribution structure, depositing a first magnetic material over a top surface and sidewalls of the first conductive via, coupling a first die and a second die to the first redistribution structure, encapsulating the first die, the second die, and the first conductive via in an encapsulant, and planarizing the encapsulant and the first magnetic material to expose the top surface of the first conductive via while a remaining portion of the first magnetic material remains on sidewalls of the first conductive via, where the first conductive via and the remaining portion of the first magnetic material provide an inductor.

A multi-chip interconnection package structure with a heat dissipation plate and a preparation method thereof are provided. The multi-chip interconnection package structure with a heat dissipation plate includes a fine circuit layer, at least one die, a heat dissipation plate, a plastic package body, and a package circuit layer, the heat dissipation plate is provided on the fine circuit layer, and is mounted on a side of the die away from the fine circuit layer, the plastic package body wraps the die and the heat dissipation plate, and the package circuit layer is provided on the plastic package body.

A semiconductor package including a redistribution layer, semiconductor devices, a semiconductor die, conductive features, an encapsulant and conductive terminals is provided. The semiconductor devices are disposed on the first surface of the redistribution layer. The semiconductor die, the conductive features, the encapsulant including openings are disposed on the second surface of the redistribution layer. The semiconductor die is embedded in the encapsulant, and the portion of the conductive features is protruded from the encapsulant. The conductive terminals including first elements disposed in the openings of the encapsulant and second elements disposed on the conductive features. A portion of the first elements and the second elements are protruded from the encapsulant, and a surface of each of the first elements opposite to the encapsulant and a surface of each of the second elements are aligned with a standoff baseline. A manufacturing method of semiconductor package is also provided.

A multilayer board includes a base including insulating layers stacked in a stacking direction, and a mounting surface at an end of the base in a first direction along the stacking direction, an electronic component inside the base, and a first heat dissipator extending through at least one of the insulating layers from a surface of the electronic component located at an end of the electronic component in the first direction to the mounting surface. When a section of the first heat dissipator is defined as a first section, and a section of the first heat dissipator located farther in a second direction along the layer stacking direction than the first section is defined as a second section, there is a combination of a first section and a second section in which the second section extends farther outward than the first section when viewed from the layer stacking direction.

A multi-chip interconnection package structure with a heat dissipation plate and a preparation method thereof are provided. The multi-chip interconnection package structure with a heat dissipation plate includes a fine circuit layer, at least one die, a heat dissipation plate, a plastic package body, and a package circuit layer, the heat dissipation plate is provided on the fine circuit layer, and is mounted on a side of the die away from the fine circuit layer, the plastic package body wraps the die and the heat dissipation plate, and the package circuit layer is provided on the plastic package body.

A multilayer board includes a base including insulating layers stacked in a stacking direction, and a mounting surface at an end of the base in a first direction along the stacking direction, an electronic component inside the base, and a first heat dissipator extending through at least one of the insulating layers from a surface of the electronic component located at an end of the electronic component in the first direction to the mounting surface. When a section of the first heat dissipator is defined as a first section, and a section of the first heat dissipator located farther in a second direction along the layer stacking direction than the first section is defined as a second section, there is a combination of a first section and a second section in which the second section extends farther outward than the first section when viewed from the layer stacking direction.

A method for forming conductive blocks on a package substrate, a semiconductor package and a method for forming the same is provided. The method for forming conductive blocks on a package substrate comprises: providing a package substrate with multiple sets of conductive pads formed thereon; depositing a solder material onto the package substrate to form solder bumps on the multiple sets of conductive pads; attaching multiple conductive blocks onto the package substrate, wherein each of the multiple conductive bloc aligned with one of the multiple sets of conductive pads; loading the package substrate on a bottom chase with the multiple conductive blocks facing upward; and pressing, with a top chase, the conductive blocks against the bottom chase to reshape the solder bumps and horizontally align top surfaces of the multiple conductive blocks with each other.

A method of forming an inductor including forming a first redistribution structure on a substrate, forming a first conductive via over and electrically connected to the first redistribution structure, depositing a first magnetic material over a top surface and sidewalls of the first conductive via, coupling a first die and a second die to the first redistribution structure, encapsulating the first die, the second die, and the first conductive via in an encapsulant, and planarizing the encapsulant and the first magnetic material to expose the top surface of the first conductive via while a remaining portion of the first magnetic material remains on sidewalls of the first conductive via, where the first conductive via and the remaining portion of the first magnetic material provide an inductor.