A package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulant and a redistribution layer. The first semiconductor die has first conductive posts and a first protection layer laterally surrounding the first conductive posts. The second semiconductor die is embedded in the first protection layer and surrounded by the first conductive posts of the first semiconductor die, wherein the second semiconductor die includes second conductive posts. The insulating encapsulant is encapsulating the first semiconductor die and the second semiconductor die. The redistribution layer is disposed on the insulating encapsulant and connected with the first conductive posts and the second conductive posts, wherein the first semiconductor die is electrically connected with the second semiconductor die through the first conductive posts, the redistribution layer and the second conductive posts.

A package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulant and a redistribution layer. The first semiconductor die has first conductive posts and a first protection layer laterally surrounding the first conductive posts. The second semiconductor die is embedded in the first protection layer and surrounded by the first conductive posts of the first semiconductor die, wherein the second semiconductor die includes second conductive posts. The insulating encapsulant is encapsulating the first semiconductor die and the second semiconductor die. The redistribution layer is disposed on the insulating encapsulant and connected with the first conductive posts and the second conductive posts, wherein the first semiconductor die is electrically connected with the second semiconductor die through the first conductive posts, the redistribution layer and the second conductive posts.

A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.

A packaging method and a packaging structure are provided. The method includes: providing a first substrate and a second substrate, the second substrate having a fist surface and a second surface opposite to each other, a side surface of the first substrate being adhered to the first surface of the second substrate via an adhesive layer; forming a groove structure on the second surface of the second substrate; providing a base, the base having a first surface and a second surface opposite to each other, the first surface of the base including a sensing region and multiple bonding pads around the sensing region; and laminating the second surface of the second substrate with the first surface of the base to form a cavity between the groove structure and the base, such that the sensing region is located in the cavity.

A package includes a die and a redistribution layer. A top surface of the die has a first area and a second area connected with the first area. The redistribution layer structure includes a first insulation layer, a redistribution layer, and a second insulation layer. The first insulation layer is overlapping with the second area. The redistribution layer is disposed above the die. The second insulation layer is disposed above the redistribution layer and overlapping with the second area and the first area. The second insulation layer covers a top surface of the first insulation layer and is in contact with a side surface of the first insulation layer and the top surface of the die.

A packaging method and a packaging structure are provided. The method includes: providing a first substrate and a second substrate, the second substrate having a first surface and a second surface opposite to each other, a side surface of the first substrate being adhered to the first surface of the second substrate via an adhesive layer; forming a groove structure on the second surface of the second substrate; providing a base, the base having a first surface and a second surface opposite to each other, the first surface of the base including a sensing region and multiple bonding pads around the sensing region; and laminating the second surface of the second substrate with the first surface of the base to form a cavity between the groove structure and the base, such that the sensing region is located in the cavity.

A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.

An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.

An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.

A semiconductor package includes a semiconductor chip comprising an active surface and an inactive surface facing each other. At least one antenna module is arranged adjacent to the semiconductor chip. The at least one antenna module comprises a main antenna and a sub-antenna. A redistribution structure is disposed on the semiconductor chip and the at least one antenna module. The redistribution structure electrically connects the active surface of the semiconductor chip to the at least one antenna module. A molding member surrounds the semiconductor chip and the at least one antenna module. The inactive surface of the semiconductor chip and the main antenna are exposed from the molding member, and the sub-antenna is covered by the molding member.