Patent classifications
H01L2224/24998
Patterned structure for electronic device and manufacturing method thereof
The present invention provides a patterned structure for an electronic device and a manufacturing method thereof. The patterned structure includes a patterned layer, a blocking structure, a cantilever structure, and a connection structure. The patterned layer is disposed on a substrate. The blocking structure is disposed on the substrate at one side of the patterned layer, wherein a thickness of the blocking structure is smaller than a thickness of the patterned layer. The cantilever structure is disposed on the substrate and located between the patterned layer and the blocking structure. The cantilever structure is connected with the patterned layer and the blocking structure. The connection structure is connected between the patterned layer and the substrate at one side of the patterned layer, and located on the cantilever structure and the blocking structure.
Electronics package with integrated interconnect structure and method of manufacturing thereof
An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.
Semiconductor package and manufacturing method thereof
A semiconductor package and a manufacturing method are provided. The semiconductor package includes a die, a dummy cube, a stress relaxation layer, an encapsulant and a redistribution structure. The dummy cube is disposed beside the die. The stress relaxation layer covers a top surface of the dummy cube. The encapsulant encapsulates the die and the dummy cube. The redistribution structure is disposed over the encapsulant and is electrically connected to the die. The stress relaxation layer is interposed between the dummy cube and the redistribution structure.
Wafer-level system packaging method and package structure
The present disclosure provides a wafer-level packaging method and a package structure. The wafer-level packaging method includes: providing a device wafer that contains a plurality of first chips, that each first chip contains a first electrode exposed at a wafer front surface of the device wafer; providing a plurality of second chips, that each second chip contains a second electrode exposed at a chip front surface of the each second chip, and a surface opposite to the chip front surface is a chip back surface; bonding the chip back surface of the each second chip to a portion of the wafer front surface of the device wafer between adjacent first chips of the plurality of first chips; forming insulating sidewalls on sidewalls of the plurality of second chips; and forming a conductive layer conformally covering the chip front surface, each insulating sidewall, and the wafer front surface.
ELECTRONIC DEVICE INCLUDING ELECTRICAL CONNECTIONS ON AN ENCAPSULATION BLOCK
An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.
SEMICONDUCTOR PACKAGE AND METHOD OF MAKING THE SAME
A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.
SEMICONDUCTOR LASER COMPONENT AND METHOD OF PRODUCING A SEMICONDUCTOR LASER COMPONENT
A semiconductor laser component including a semiconductor chip arranged to emit laser radiation, a cladding that is electrically insulating and covers the semiconductor chip in places, and a bonding layer that electrically conductively connects the semiconductor chip to a first connection point, wherein the semiconductor chip includes a cover surface, a bottom surface, a first front surface, a second front surface, a first side surface and a second side surface, the first front surface is arranged to decouple the laser beam, the cladding covers the semiconductor chip at least in places on the cover surface, the second front surface, the first side surface and the second side surface, and the bonding layer on the cladding extends from the cover surface to the first connection point.
Semiconductor chip packaging structure without soldering wire, and packaging method thereof
A semiconductor chip packaging structure without soldering wire and a packaging method thereof are disclosed. The semiconductor chip packaging structure comprises at least one packaging structure, and each packaging structure comprises a substrate, and a semiconductor chip is arranged on the substrate. Pins of the semiconductor chip are electrically connected to the conductive circuit formed by engraving or etching metal film or alloy film. The semiconductor chip packaging structure also comprises a packaging glue layer covering the semiconductor chip and the conductive circuit. The semiconductor chip packaging method includes steps of arranging a semiconductor chip on the substrate; forming a metal film or an alloy film around the semiconductor chip; etching the metal film or alloy film, to form the conductive circuit; and covering a packaging glue layer on the semiconductor chip and the conductive circuit. As a result, the production efficiency can be improved greatly.
STACK OF ELECTRICAL COMPONENTS AND METHOD OF PRODUCING THE SAME
A stack of electrical components has a first electrical component having a first surface, a second surface that is opposite to the first surface and a side surface that is located between the first surface and the second surface; a second electrical component having a third surface on which the first electrical component is mounted, the third surface facing the second surface and forming a corner portion between the third surface and the side surface; an adhesive layer that bonds the first electrical component to the second electrical component, wherein the adhesive layer has a first portion that is located between the second surface and the third surface and a curved second portion that fills the corner portion; and a conductive layer that extends on a side of the side surface, curves along the second portion and extends to the third surface.
SEMICONDUCTOR CHIP PACKAGING STRUCTURE WITHOUT SOLDERING WIRE, AND PACKAGING METHOD THEREOF
A semiconductor chip packaging structure without soldering wire and a packaging method thereof are disclosed. The semiconductor chip packaging structure comprises at least one packaging structure, and each packaging structure comprises a substrate, and a semiconductor chip is arranged on the substrate. Pins of the semiconductor chip are electrically connected to the conductive circuit formed by engraving or etching metal film or alloy film. The semiconductor chip packaging structure also comprises a packaging glue layer covering the semiconductor chip and the conductive circuit. The semiconductor chip packaging method includes steps of arranging a semiconductor chip on the substrate; forming a metal film or an alloy film around the semiconductor chip; etching the metal film or alloy film, to form the conductive circuit; and covering a packaging glue layer on the semiconductor chip and the conductive circuit. As a result, the production efficiency can be improved greatly.