A semiconductor package includes an outer redistributed line (RDL) structure, a first semiconductor chip disposed on the outer RDL structure, a stack module stacked on the first semiconductor chip, and a bridge die stacked on the outer RDL structure. A portion of the stack module laterally protrudes from a side surface of the first semiconductor chip. The bridge die supports the protruding portion of the stack module. The stack module includes an inner RDL structure, a second semiconductor chip disposed on the inner RDL structure, a capacitor die disposed on the inner RDL structure, and an inner encapsulant. The capacitor die acts as a decoupling capacitor of the second semiconductor chip.

A display device includes an active region, a pad region adjacent to the active region, a first peripheral region between the active region and the pad region, a second peripheral region outside the active region and spaced apart from the pad region, a base layer, a circuit layer on the base layer, a light-emitting element layer on the circuit layer and corresponding to the active region, a capping layer on the light-emitting element layer, a dam part extended along the active region and in the first peripheral region and the second peripheral region, and a protruding part outside the dam part in the second peripheral region and on the base layer.

A display device may include: a first power line and a second power line located on a substrate; a first electrode electrically connected to the first power line through a first contact portion; a second electrode electrically connected to the second power line through a second contact portion and spaced apart from the first electrode in a first direction; a light emitting element located on the first electrode and the second electrode; and a pixel circuit including a transistor and a storage capacitor, and electrically connected to the light emitting element. The first contact portion may include a plurality of first contact portions successively arranged in the first direction. In a plan view, the storage capacitor may have a shape extending in a second direction different from the first direction.

A display device includes a first electrode and a second electrode, spaced apart from each other; light emitting elements disposed between the first electrode and the second electrode; a first connection electrode electrically contacting the first electrode and first end portions of the light emitting elements; a second connection electrode electrically contacting the second electrode and second end portions of the light emitting elements; and a conductive pattern disposed between the first connection electrode and the second connection electrode. A first end portion of the conductive pattern electrically contacts the first connection electrode, and a second end portion of the conductive pattern electrically contacts the second connection electrode.

A display device includes first banks extending in a first direction and that are spaced apart from each other in a second direction intersecting the first direction, a first electrode extending in the first direction and including a first part disposed between the first banks, a second electrode extending in the first direction and including a second part spaced apart from the first part in the second direction and disposed between the first banks, a first dummy pattern disposed on one of the first banks and spaced apart from the first part, a second dummy pattern disposed on another one of the first banks and spaced apart from the second part, and light-emitting elements disposed between the first banks, the light-emitting elements having at least one end portion disposed on one of the first part of the first electrode and the second part of the second electrode.

A display panel manufacturing apparatus and a display panel manufacturing method are provided. A display panel manufacturing apparatus manufactures a display panel which is on a lower stage and includes light emitting elements. The display panel manufacturing apparatus includes: a power supply for supplying an alignment voltage for aligning the light emitting elements on the display panel; and an upper stage including a probe unit to provide the alignment voltage to the display panel and magnetic sensors to sense an alignment state of the light emitting elements.

A display device includes a first conductive layer including a first voltage line and a second voltage line, a buffer layer, a semiconductor layer including a first active layer and a second active layer, a first gate insulating layer, a second conductive layer including a first gate electrode overlapping the first active layer and a second gate electrode overlapping the second active layer, a passivation layer, a via layer, a bank pattern layer including a first bank pattern and a second bank pattern partially spaced apart from each other, a third conductive layer including a first electrode and a second electrode spaced apart from each other, and light emitting elements. The passivation layer includes silicon nitride (SiN.sub.x), and a ratio of a number of silicon-hydrogen bonds (Si—H) to a number of nitrogen-hydrogen bonds (N—H) in the silicon nitride (SiN.sub.x) is in a range of about 1:0.6 to about 1:1.5.

A semiconductor component includes at least two functional units which are identical to one another and are wired to one another, the identical functional units each include at least one gate finger, at least one source finger and at least one drain finger; the wiring comprising conductor tracks. A first track connects the gate fingers respectively, a second track connects the source fingers respectively, and a third track connects the drain fingers of the at least two same functional units, respectively.

A display device may include a light emitting element including a first end having a first surface, and a second end having a second surface parallel to the first surface, an organic pattern that overlaps the light emitting element and exposes the first and second surfaces, a first electrode disposed on a substrate and electrically contacting the first end, and a second electrode disposed on the substrate and spaced apart from the first electrode, and electrically contacting the second end. A surface area of the first surface may be less than that of the second surface. A top surface of the organic pattern may be a curved surface.

A multichip module comprises a carrier, a plurality of chips, an electrical insulating layer, and an electrical interconnect structure. The carrier includes a bottom wall and four side walls defining an internal cavity. The chips are positioned in the internal cavity, with each chip including a plurality of bond pads. The electrical insulating layer is formed from electrically insulating material and is positioned on an upper surface of the carrier and the chips. The electrical interconnect structure includes a plurality of interconnect traces, with each interconnect trace formed from electrically conductive material and electrically connected to a first bond pad on a first chip and a second bond pad on a second chip. Each interconnect trace includes a bridge having a segment that is spaced apart from, and positioned above, the electrical insulating layer.