A connecting member includes a first part arranged between a first region of an electronic device and a board and a second part arranged between a second region of the electronic device and the board, a distance from an edge to the first part is longer than a distance from a center to the first part, and a distance from the edge to the second part is shorter than a distance from the center to the second part, a space is provided between the electronic device and the board and between the first part and the second part, and, in the board, a through hole communicating with the space is provided not to overlap with the center of the electronic device.

Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

A bonding member (10) includes surface-processed silver surfaces (11a, 11b).

Disclosed herein are a light emitting device package, a backlight unit, an illumination apparatus, and a method of manufacturing a light emitting device package capable of being used for a display application or an illumination application. The light emitting device package includes: a flip-chip type light emitting device having a first terminal and a second terminal installed therebeneath; a substrate having a first electrode formed at one side of an electrode separating space and a second electrode formed at the other side thereof; a first conductive bonding member installed on the first electrode of the substrate so as to be electrically connected to the first terminal of the light emitting device; a second conductive bonding member installed on the second electrode of the substrate so as to be electrically connected to the second terminal of the light emitting device; a reflection encapsulant molded and installed on the substrate so as to form a reflection cup part reflecting light generated in the light emitting device and filled in the electrode separating space to form an electrode separating part; and a filler filled between the reflection cup part and the first and second conductive bonding members.

Embodiments described herein provide for a pH sensor that comprises a substrate and an ion sensitive field effect transistor (ISFET) die. The ISFET die includes an ion sensing part that is configured to be exposed to a medium such that it outputs a signal related to the pH level of the medium. The ISFET die is bonded to the substrate with at least one composition of bonding agent material disposed between the ISFET die and the substrate. One or more strips of the at least one composition of bonding agent material is disposed between the substrate and the ISFET die in a first pattern.

In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.

Structures, materials, and methods to control the spread of a solder material or other flowable conductive material in electronic and/or electromagnetic devices are provided.

Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

A package structure is provided. The package structure includes a chip structure and a first adhesive element partially covering the chip structure. The first adhesive element has a first portion and a second portion, and the first portion is spaced apart from the second portion. The first adhesive element has a first thermal conductivity. The package structure also includes a second adhesive element partially covering the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is higher than the first thermal conductivity.

A sensor packaging method and a sensor package are provided. The method includes: providing a substrate having upper and lower board surfaces, in which the upper board surface has a die-bonding region. The substrate includes a core material layer, an upper metal layer, and an upper protection layer, a first window is formed to penetrate the upper protection layer and located at a periphery of the die-bonding region, and the first window is opened for a first ground electrode connected to a first ground portion. The method further includes: performing a dispensing step to apply an adhesive material on the upper board surface in at least a portion of the die-bonding region; and attaching a sensor die to the substrate through the adhesive material, in which the sensor die is disposed in the die-bonding region and has a first ground pin electrically connected to the first ground electrode.