A semiconductor package structure and manufacturing method thereof are provided, and the semiconductor package structure includes a semiconductor element, a top substrate, a bottom substrate, an insulating layer, and two metal conductive layers. The top substrate is mainly made of a conductive metal, and having a first separated portion on the top substrate, the first separated portion divides the top substrate into two blocks which are not electrically connected to each other. The bottom substrate is mainly made of the conductive metal, and having a second separated portion on the bottom substrate. The second separated portion divides the bottom substrate into two blocks which are not electrically connected to each other. The insulating layer is disposed between the top substrate and the bottom substrate. The metal conductive layer is disposed at two sides of the insulating layer and connected to the top substrate and the bottom substrate. The semiconductor element is contacted with the top substrate and the bottom substrate.

A semiconductor substrate (1) has a front surface and a back surface that are opposite each other. A first metal layer (2) is formed on the front surface of the semiconductor substrate (1). A second metal layer (3) for soldering is formed on the first metal layer (2). A third metal layer (5) is formed on the back surface of the semiconductor substrate (1). A fourth metal layer (6) for soldering is formed on the third metal layer (5). The second metal layer (3) has a larger thickness than that of the fourth metal layer (6). The first, third, and fourth metal layers (2, 5, 6) are not divided in a pattern. The second metal layer (3) is divided in a pattern and has a plurality of metal layers electrically connected to each other via the first metal layer (2).

Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate. The method also includes disposing a semiconductor die over the carrier substrate such that the conductive structures surround the semiconductor die. The method further includes forming a protective layer to surround the conductive structures and the semiconductor die. In addition, the method includes disposing a shielding element over the semiconductor die and the conductive structures. The shielding element is electrically connected to the conductive structures.

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a first substrate; a first adhesive layer disposed on the surface of the first substrate; a first buffer layer disposed on the surface of the first adhesive layer; and a first bonding layer disposed on the surface of the first buffer layer, wherein the densities of the first adhesive layer and the first buffer layer are greater than that of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and the first buffer layer, and the first buffer layer and the first bonding layer exhibit higher adhesion, which are beneficial to improve the performance of the semiconductor structure.

The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first substrate; a first adhesive layer disposed on a surface of the first substrate; and a first bonding layer disposed on a surface of the first adhesive layer. A density of the first adhesive layer is greater than a density of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and first bonding layer, such that it is advantageous to improve a performance of the semiconductor structure.

A semiconductor device includes: a first conductive plate and a second conductive plate spaced apart from each other in a direction x; a third conductive plate facing the first and second conductive plates in a direction z; a first semiconductor element arranged between the first conductive plate and the third conductive plate; a second semiconductor element arranged between the second conductive plate and the third conductive plate; a positive input terminal electrically connected to the first conductive plate; a negative input terminal electrically connected to the second conductive plate; an output terminal electrically connected to the third conductive plate; and a sealing resin covering at least the first and second semiconductor elements.

Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

A method of transferring micro devices is provided. A carrier substrate including a buffer layer and a plurality of micro devices is provided. The buffer layer is located between the carrier substrate and the micro devices. The micro devices are separated from one another and positioned on the carrier substrate through the buffer layer. A receiving substrate contacts the micro devices disposed on the carrier substrate. A temperature of at least one of the carrier substrate and the receiving substrate is changed, so that at least a portion of the micro devices are released from the carrier substrate and transferred onto the receiving substrate. A number of the at least a portion of the micro devices is between 1000 and 2000000.

In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

A semiconductor package includes a first semiconductor die, second semiconductor dies each of which has a width less than a width of the first semiconductor die and which are stacked on the first semiconductor die, a first non-conductive layer between the first semiconductor die and a lowermost second semiconductor die, and a second non-conductive layer between adjacent ones of the second semiconductor dies. Each of the second semiconductor dies includes a first substrate that has a first front surface and a first rear surface, a first interlayer dielectric layer that covers the first front surface, first through electrodes that penetrate the first substrate, and a first passivation layer that covers the first rear surface. A first groove is in the first passivation layer and a portion of the first substrate. The second non-conductive layer is within the first groove.