In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.

The present disclosure provides devices and methods in which a semiconductor chip has a reduced size and thickness. The device is manufactured by utilizing a sacrificial or dummy silicon wafer. A recess is formed in the dummy silicon wafer where the semiconductor chip is mounted in the recess. The space between the dummy silicon wafer and the chip is filled with underfill material. The dummy silicon wafer and the backside of the chip are etched using any suitable etching process until the dummy silicon wafer is removed, and the thickness of the chip is reduced. With this process, the overall thickness of the semiconductor chip can be thinned down to less than 50 μm in some embodiments. The ultra-thin semiconductor chip can be incorporated in manufacturing flexible/rollable display panels, foldable mobile devices, wearable displays, or any other electrical or electronic devices.

In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.

A semiconductor package includes: a first package substrate; a first semiconductor device mounted on the first package substrate; a second package substrate arranged on an upper part of the first semiconductor device; and a heat-dissipating material layer arranged between the first semiconductor device and the second package substrate and having a thermal conductivity of approximately 0.5 W/m.Math.K to approximately 20 W/m.Math.K, wherein the heat-dissipating material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second package substrate.

An integrated circuit (IC) package includes a first die with a first surface overlaying a substrate. The first die includes a first metal pad at a second surface opposing the first surface. The IC package also includes a dielectric layer having a first surface contacting the second surface of the first die. The IC package further includes a second die with a surface that contacts a second surface of the dielectric layer. The second die includes a second metal pad aligned with the first metal pad of the first die. A plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.

An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

A bridge embedded interposer and a package substrate and a semiconductor package including the same includes: a connection structure including one or more redistribution layers, a first bridge disposed on the connection structure and including one or more first circuit layers electrically connected to the one or more redistribution layers, a frame disposed around the first bridge on the connection structure and including one or more wiring layers electrically connected to the one or more redistribution layers, and an encapsulant disposed on the connection structure and covering at least a portion of each of the first bridge and the frame.

A method comprises: providing a layer of curable adhesive material (4) on a substrate (2); forming a pattern of microstructures (321) on the layer of curable adhesive material (4); curing a first region (42) of the layer of curable adhesive material (4) at a first level and a second region (44) of the layer of curable adhesive material (4) at a second level greater than the first level; providing a solid circuit die (6) to directly attach to a major surface of the first region (42) of the layer of curable adhesive material (4); and further curing the first region (42) of the layer of curable adhesive material (4) to anchor the solid circuit die (6) on the first region (42) by forming an adhesive bond therebetween. The pattern of microstructures (321) may include one or more microchannels (321), the method further comprising forming one or more electrically conductive traces in the microchannels (321), in particular, by flow of a conductive particle containing liquid (8) by a capillary force and, optionally, under pressure. The at least one microchannel (321) may extend from the second region (44) to the first region (42) and have a portion beneath the solid circuit die (6). The solid circuit die (6) may have at least one edge disposed within a periphery of the first region (42) with a gap therebetween. The solid circuit die (6) may have at least one contact pad (72) on a bottom surface thereof, wherein the at least one contact pad (72) may be in direct contact with at least one of the electrically conductive traces in the microchannels (321). Forming the pattern of microstructures (321) may comprise contacting a major surface of a stamp (3) to the layer of curable adhesive material (4), the major surface having a pattern of raised features (32) thereon. The curable adhesive material (4) may be cured by an actinic light source such as an ultraviolet (UV) light source (7, 7′), wherein a mask may be provided to at least partially block the first region (42) of the layer of curable adhesive material (4) from the cure. The stamp (3) may be positioned in contact with the curable adhesive material (4) to replicate the pattern of raised features (32) to form the microstructures (321) while the curable adhesive material (4) is selectively cured by the actinic light source such as the ultraviolet (UV) light source (7). The first region (42) of the layer of curab

A flip chip package unit and associated packaging method. The flip chip package unit may include an integrated circuit (“IC”) die having a plurality of metal pillars formed on its first surface and attached to a rewiring substrate with the first surface of the IC die facing to the rewiring substrate, an under-fill material filling gaps between the first surface of the IC die and the rewiring substrate, and a thermal conductive protection film covering or overlaying and directly contacting with the entire second die surface and a first portion of sidewalls of the IC die. The thermal conductive protection film may have good thermal conductivity, uneasy to fall off from the IC die and can provide physical protection, electromagnetic interference protection and effective heat dissipation path to the IC die.

A flip chip package unit and associated packaging method. The flip chip package unit may include an integrated circuit (“IC”) die having a plurality of metal pillars formed on its first surface and attached to a rewiring substrate with the first surface of the IC die facing to the rewiring substrate, an under-fill material filling gaps between the first surface of the IC die and the rewiring substrate, and a back protective film attached to a second surface of the IC die. The back protective film may have good UV sensitivity to change from non-solid to solid after UV irradiation while maintaining its viscosity with the IC die not reduced after UV irradiation. The back protective film may be uneasy to deform and to peel off from the IC die and can provide physical protection and effective heat dissipation path to the IC die.