A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, an under-fill fillet on side surfaces of the plurality of semiconductor devices, and a molding resin surrounding the plurality of semiconductor devices. An uppermost end of the under-fill fillet includes a planar surface coplanar with an upper surface of a periphery of an uppermost semiconductor device among the plurality of semiconductor devices, and the molding resin completely covers the planar surface.

A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

A semiconductor device includes: a first semiconductor element; a second semiconductor element; a first insulating base member adhesively bonded to the first semiconductor element; a first wiring connected to a first electrode of the first semiconductor element, and disposed on the first insulating base member; a second insulating base member adhesively bonded to the second semiconductor element, a second wiring connected to a third electrode of the second semiconductor element, and disposed on the second insulating base member; a first wiring member connected to a second electrode of the first semiconductor element; a second wiring member electrically connected to the first wiring and a fourth electrode of the second semiconductor element; and a third wiring member connected to the second wiring. A current flows in a first direction in the first wiring member, and flows in a second direction opposite to the first direction in the third wiring member.

A semiconductor device includes an insulated circuit board having a conductive pattern layer, a sintered member disposed on the conductive pattern layer, a semiconductor chip placed on the sintered member, and a coating material covering the semiconductor chip. The sintered member has, on a surface thereof opposite to the conductive pattern layer, a frame shaping the outer edge of a recess. The semiconductor chip is mounted in the recess such that its top face is located closer to the conductive pattern layer than a top end of the frame.

A semiconductor device includes: a semiconductor base body; a semiconductor chip; a sintering material layer bonded to a lower surface of the semiconductor chip and having a thickness decreasing toward an outer periphery of the semiconductor chip; and a conductive plate having a main surface facing the lower surface of the semiconductor chip and a recessed portion which the sintering material layer contacts in the main surface, the recessed portion having a depth decreasing toward the outer periphery of the semiconductor chip.

A semiconductor arrangement includes a semiconductor substrate having a dielectric insulation layer and at least a first metallization layer arranged on a first side of the dielectric insulation layer. The first metallization layer includes at least two sections, each section being separated from a neighboring section by a recess. A semiconductor body is arranged on one of the sections of the first metallization layer. At least one indentation is arranged between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.

A semiconductor device includes a first lead portion and a second lead portion spaced from each other in a first direction. A semiconductor chip is mounted to the first lead portion. A first connector has a first portion contacting a second electrode on the chip and a second portion connected to the second lead portion. A second connector has third portion that contacts the second electrode, but at a position further away than the first portion, and a fourth portion connected to the second portion. At least a part of the second connector overlaps a part of the first connector between the first lead portion and the second lead portion.

A chip packaging structure and a method for preparing the same, and a method for packaging a semiconductor structure are provided, which relate to the technical field of semiconductors, and solve the technical problem of low yield of a chip. The chip packaging structure includes: a chip, an intermediate insulating layer arranged on the chip and a non-conductive adhesive layer arranged on the intermediate insulating layer, where a plurality of conductive pillar bumps are arranged on the chip, and each conductive pillar bump penetrates through the intermediate insulating layer; the intermediate insulating layer is provided with at least one group of holding holes, and the non-conductive adhesive layer fills the holding holes, so that grooves respectively matched with the holding holes are formed in a surface, far away from the intermediate insulating layer, of the non-conductive adhesive layer.

A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate and that includes a first semiconductor substrate that includes through electrodes, and a second semiconductor chip disposed on the first semiconductor chip and that includes a second semiconductor substrate that includes an active surface and an inactive surface. The second semiconductor chip further includes a plurality of isolated heat dissipation fins that extend in a vertical direction from the inactive surface.