A bonded body is provided including: a bonding layer containing Cu; and a semiconductor element bonded to the bonding layer. The bonding layer includes an extending portion laterally extending from a peripheral edge of the semiconductor element. In a cross-sectional view in a thickness direction, the extending portion rises from a peripheral edge of a bottom of the semiconductor element or from the vicinity of the peripheral edge of the bottom of the semiconductor element, and includes a side wall substantially spaced apart from a side of the semiconductor element. Preferably, the extending portion does not include any portion where the side wall and the side of the semiconductor element are in contact with each other. A method for manufacturing a bonded body is also provided.

An object of the present invention is to provide a semiconductor device in which peeling between a mold resin and a substrate is suppressed. A semiconductor device 1 includes a semiconductor chip 20 and a substrate 10 that are molded with a mold resin layer 40. The semiconductor device 1 includes a resin layer 50 having a thickness of 200 nm or less different from the mold resin layer 40 between the cured mold resin layer 40 and the substrate 10. The resin layer 50 present between the mold resin layer 40 and the substrate 10 is preferably present on a periphery of 30% or more of the chip when an entire peripheral length of the chip is 100%.

Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconductor chip and an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate, and a recess region between the central part and the edge part. The recess region may be defined by a sidewall of the central part, a sidewall of the edge part, and a top surface of the conductive line in the lower substrate.

Disclosed is a semiconductor package comprising a first semiconductor chip on a substrate, a second semiconductor chip between the substrate and the first semiconductor chip, and a spacer between the substrate and the first semiconductor chip. The substrate includes a first substrate pad between the second semiconductor chip and the spacer. The second semiconductor chip includes a chip pad and a signal wire. The spacer includes a first dummy pad on the spacer and a first dummy wire coupled to the first dummy pad. The first dummy pad is adjacent to the second semiconductor chip. The first semiconductor chip is attached to the second semiconductor chip and the spacer by an adhesive layer on the first semiconductor chip. A portion of each of the signal wire and the first dummy wire are in the adhesive layer.

Devices and method for forming a chip package structure including at least one semiconductor die attached to a redistribution structure, a molding compound die frame laterally surrounding the at least one semiconductor die, and a first underfill material portion located between the redistribution structure and the at least one semiconductor die and contacting sidewalls of the at least one semiconductor die and sidewalls of the molding compound die frame. The first underfill material portion may include at least one cut region, in which the first underfill material portion may include a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.

A semiconductor package includes a circuit board, an interposer structure on the circuit board, a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees.

An electronic device includes a substrate, a base substrate, a metal connection body, a metal body, and a via. The substrate includes a first main surface provided with functional elements and is a piezoelectric substrate or a compound semiconductor substrate. The substrate is mounted on the base substrate such that a second main surface of the substrate opposite to the one main surface faces the base substrate. The metal body is provided at the first main surface of the substrate and includes at least a portion that extends to outside the substrate in plan view from the one main surface. The via connects the portion of the metal body outside the substrate and the base substrate to each other and has a higher thermal conductivity than the substrate.

A semiconductor device has a first substrate including an element region, a peripheral region that surrounds the element region, a first insulator with a first recess portion in the peripheral region, a first metal layer in the element region, and a first conductor in the peripheral region to surround the element region. A second substrate has an element region, a peripheral region that surrounds the element region, a second insulator with a second recess portion that faces the first recess portion, a second metal layer in contact with the first metal layer, and a second conductor that surrounds the element region of the second substrate.

A semiconductor device has a first substrate including an element region, a peripheral region that surrounds the element region, a first insulator with a first recess portion in the peripheral region, a first metal layer in the element region, and a first conductor in the peripheral region to surround the element region. A second substrate has an element region, a peripheral region that surrounds the element region, a second insulator with a second recess portion that faces the first recess portion, a second metal layer in contact with the first metal layer, and a second conductor that surrounds the element region of the second substrate.

A semiconductor package includes a leadframe having a die pad and a plurality of pins disposed around the die pad, a metal interposer attached to a top surface of the die pad, and a semiconductor die attached to a top surface of the metal interposer. A plurality of bond wires with same function is bonded to the metal interposer. The die pad, the metal interposer and the semiconductor die are stacked in layers so as to form a pyramidal stack structure.