A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

Semiconductor packages and methods of forming the same are disclosed. a semiconductor package includes a die and an underfill. The die is disposed over a surface and includes a first sidewall. The underfill encapsulates the die. The underfill includes a first underfill fillet on the first sidewall, and in a cross-sectional view, a second sidewall of the first underfill fillet has a turning point.

A process of forming a semiconductor device is disclosed, where the semiconductor device provides a substrate. The process includes steps of: (a) depositing a first metal layer containing nickel (Ni) on a secondary surface of the substrate and within a substrate via provided in the substrate; (b) depositing a second metal layer on the first metal layer by electrolytic plating; (c) depositing a third metal layer on the second metal layer, where the third metal layer contains at least one of Ni and titanium (Ti); (d) exposing the second metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the third metal layer; and (e) die-bonding the semiconductor device on an assembly substrate by interposing solder between the secondary surface of the substrate and the assembly substrate.

An electronic device module includes a substrate having a ground region including ground pads spaced apart from each other, an electronic device mounted on the substrate and including a ground terminal bonded to the ground region, and a conductive adhesive bonding the ground pads and the ground terminal together, wherein an upper surface of the conductive adhesive includes a bonding surface bonded to the ground terminal, and a lower surface of the conductive adhesive includes bonding surfaces bonded to each of the ground pads, and an air path provided between the ground pads, through which gas generated in a process of mounting the electronic device on the substrate is discharged.

A semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. A side surface of the first adhesive layer is recessed from side surfaces of the first and second semiconductor chips.

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

A method for manufacturing a semiconductor device of an embodiment includes: dividing a semiconductor wafer including a plurality of chip areas each having a columnar electrode and dicing areas, along the dicing areas to form a plurality of semiconductor chips; sticking a first resin film on the plurality of semiconductor chips while filling parts of the first resin film in gaps each present between adjacent ones of the plurality of semiconductor chips; forming trenches narrower in width than the gaps in the first resin film filled in the gaps; and sequentially picking up the plurality of semiconductor chips each having the first resin film, and mounting the picked semiconductor chip on a substrate.

A bonded assembly includes an interposer including redistribution wiring interconnects and redistribution insulating layers and including recesses in corner regions. The recesses include surfaces that are recessed relative to a horizontal plane including a horizontal surface of the interposer. A least one semiconductor die is attached to the interposer through a respective array of solder material portions. An underfill material portion is located between the interposer and the at least one semiconductor die. The underfill material includes downward-protruding anchor portions that protrude downward from a horizontally-extending portion of the underfill material portion that laterally surrounds each array of solder material portions into the recesses.

Embodiments may relate to a microelectronic package that includes a die, a thermal interface material (TIM) coupled with the die, and an integrated heat spreader (IHS) coupled with the TIM. The IHS may include a feature with a non-uniform cross-sectional profile that includes a thin point and a thick point as measured in a direction perpendicular to a face of the die to which the TIM is coupled. Other embodiments may be described or claimed.

Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.