Disclosed herein are lids for integrated circuit (IC) packages with solder thermal interface materials (STIMs), as well as related methods and devices. For example, in some embodiments, an IC package may include a STIM between a die of the IC package and a lid of the IC package. The lid of the IC package may include nickel, the IC package may include an intermetallic compound (IMC) between the STIM and the nickel, and the lid may include an intermediate material between the nickel and the IMC.

A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.

A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.

Implementations of a semiconductor package may include a pin coupled to a substrate. The pin may include a titanium sublayer, a nickel sublayer, and one of a silver and tin intermetallic layer or a copper and tin intermetallic layer, the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer having a melting temperature greater than 260 degrees Celsius. The one of the silver and tin intermetallic layer or the copper and tin intermetallic layer may be formed by reflowing a tin layer and one of a silver layer or copper layer with a silver layer of the substrate where the substrate may be directly coupled to the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer. The substrate may include a copper layer that was directly coupled with the silver layer before the reflow.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

Provided is a semiconductor package including: a pad substrate on which a semiconductor chip is installed; a solder formed on the pad substrate having a length same as or longer than a side of the semiconductor chip; and an intagliated groove formed on the pad substrate having a length longer than at least the side of the semiconductor chip and filled with at least a certain amount of melted solder, wherein the solder having a thickness of at least 1 μm or above is filled in the intagliated groove to have a length of at least 3 μm or above and an intermetallic compound layer is formed on a certain area included in an inner wall of the intagliated groove. Accordingly, movement of the semiconductor chip may be restricted so that the quality of following processes may be improved, and electrical and mechanical combination between the solder and the pad substrate may be stabled.

Provided is a semiconductor package including: a pad substrate on which a semiconductor chip is installed; a solder formed on the pad substrate having a length same as or longer than a side of the semiconductor chip; and an intagliated groove formed on the pad substrate having a length longer than at least the side of the semiconductor chip and filled with at least a certain amount of melted solder, wherein the solder having a thickness of at least 1 μm or above is filled in the intagliated groove to have a length of at least 3 μm or above and an intermetallic compound layer is formed on a certain area included in an inner wall of the intagliated groove. Accordingly, movement of the semiconductor chip may be restricted so that the quality of following processes may be improved, and electrical and mechanical combination between the solder and the pad substrate may be stabled.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.