This disclosure relates to a discrete cascode semiconductor device and associated method of manufacture, the device includes: a high voltage depletion mode device die having gate, source and drain terminals arranged on a first major surface thereof; a low voltage enhancement mode device die having a gate and a source terminal formed on a first major surface thereof, and a drain terminal formed on a second major surface opposite the first major surface. The drain terminal of the high voltage device die is mounted on a drain connection; the source terminal of the low voltage device die and the gate terminal of the high voltage device are mounted on a common source connection; and the drain terminal of the low voltage device die is mounted on the source terminal of the high voltage device.

A power converter includes: at least one pair of first and second semiconductor devices including multiple first and second semiconductor chips, having first and second switching elements providing upper and lower arms, and multiple first and second main terminals having at least one of multiple first and second high potential terminals and multiple first and second low potential terminals; and a bridging member providing an upper and lower coupling portion, together with the first low and second high potential terminals. The first and second semiconductor chips are arranged in line symmetry with respect to first and second axes and in line symmetry with the second axis as a symmetry axis to differentiate the arrangement of the second low potential terminal with respect to the second high potential terminal from the arrangement of the first low potential terminal with respect to the first high potential terminal.

An integrated circuit includes a lead frame, a first die, and a second die. The first die is bonded to and electrically connected to the lead frame. The second die is electrically connected to and spaced apart from the first die.

According to one embodiment, a semiconductor device includes a substrate, first stacked components, second stacked components, and a coating resin. The first stacked components include first chips and are stacked on a surface of the substrate. The second stacked components include second chips and are stacked on the surface. The coating resin covers the surface, the first stacked components, and the second stacked components. A first top surface of a second farthest one of the first chips away from the surface differs in position in a first direction from a second top surface of second farthest one of the second chips away from the surface.

Provided is an electric power converter, including: a casing; a heat radiating plate having a first main surface and a second main surface; and a substrate which is fixed to the main surface and to which a heat generating component is mounted, wherein the casing has an inner wall surface in which a first tapered portion is formed, wherein the heat radiating plate includes a second tapered portion which is connected to the first tapered portion in a heat exchangeable manner and slid with respect to the first tapered portion, wherein the heat radiating plate is configured to be displaced in a first direction with respect to the casing by the second tapered portion being slid with respect to the first tapered portion, and wherein the heat generating component is connected to the casing in a heat exchangeable manner by the heat radiating plate being displaced in the first direction.

This disclosure relates to a cascode HEMT semiconductor device including a lead frame, a die pad attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.

A semiconductor sub-assembly and a semiconductor power module capable of having the reduced thickness of a chip and reduced thermal resistance are provided. The semiconductor sub-assembly includes a single or a plurality of semiconductor chips having a first electrode that is formed on the lower surface thereof, a second electrode that is formed on the upper surface thereof, and a plurality of chip-side signal electrode pads that are formed at one end of the upper surface thereof. The semiconductor chip is embedded in the embedded structure and a plurality of extension signal electrode pads are connected to each of the chip-side signal electrode pads. The extension signal electrode pad is formed on the embedded substrate in a size greater than the chip-side signal electrode pad when viewed on the plane.

Methods, systems, and apparatuses for a power card for use in a vehicle. The power card includes an N lead frame, a P lead frame, and an O lead frame each having a body portion and a terminal portion. The O lead frame is located between the N lead frame and the P lead frame. The power card includes a first power device located between the N lead frame and the O lead frame, with a first side coupled to the body portion of the N lead frame and a second side coupled to the body portion of the O lead frame. The power card includes a second power device located between the O lead frame and the P lead frame, with a first side coupled to the body portion of the O lead frame and a second side coupled to the body portion of the P lead frame.

A method for producing a power semiconductor system includes packaging a power device in plastic to form a power semiconductor component, forming a first heat dissipation face on a surface of the power semiconductor component; heating a first material between a first heat sink and the first heat dissipation face; and cooling the first material on the first heat dissipation face to connect the power semiconductor component and the first heat sink.

A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/−30 μm at the first side of the power module.