An apparatus includes a wafer portion and a plurality of die fabricated in the wafer portion in a defined pattern such that the die are separated from each other by a dicing area or a street. The apparatus includes a conductive connection between given adjacent die. The conductive connection is electrically coupled to circuitry disposed on the given adjacent die.

Provided is a coupled semiconductor package including at least two substrate pads; at least one semiconductor chip installed on each of the substrate pads; at least one terminal each of which is electrically connected to each substrate pad and each semiconductor chip; and a package housing covering a part of the at least one semiconductor chip and the at least one terminal, wherein lower surfaces of one or more substrate pads are formed to be electrically connected and lower surfaces of another one or more substrate pads are formed to be electrically insulated. Accordingly, partial insulation may be economically realized without applying an insulating material to a heat sink, when the package is joined to the heat sink.

Provided is a coupled semiconductor package including at least two substrate pads; at least one semiconductor chip installed on each of the substrate pads; at least one terminal each of which is electrically connected to each substrate pad and each semiconductor chip; and a package housing covering a part of the at least one semiconductor chip and the at least one terminal, wherein lower surfaces of one or more substrate pads are formed to be electrically connected and lower surfaces of another one or more substrate pads are formed to be electrically insulated. Accordingly, partial insulation may be economically realized without applying an insulating material to a heat sink, when the package is joined to the heat sink.

Provided are: a sintering binder including nanoparticles, a method for producing the sintering binder, and a method for bonding using the sintering binder. The sintering binder mainly includes cuprous oxide nanoparticles, combines particle stability with bondability, and less undergoes ion migration. A composite particle including metallic copper with the remainder being cuprous oxide and inevitable impurities is used for bonding typically of metals. The composite particle structurally includes metallic copper dispersed inside the particle and has an average particle size of 1000 nm or less.

A method for manufacturing a semiconductor module includes the step of soldering two or more semiconductor elements having substrate materials and heights different from each other to a metal foil disposed at one side of an insulating substrate; connecting a plurality of wiring members, not interconnecting the semiconductor elements, to front face electrodes of the semiconductor elements through solder so that heights from a surface of the insulating substrate to top faces of the wiring members become same level with each other; inspecting a leakage current while applying electricity on each one of semiconductor elements individually through the wiring members; and connecting the top faces of the wiring members with a bus bar.

A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

A method to connect power terminals to substrates within semiconductor packages is disclosed. The power terminal connection method minimally adapts the power terminal so that laser treatment can be used to connect the power terminal to the substrate. The power terminal may be adapted in a variety of ways, such that an interface between the power terminal and the substrate may be transformed (melted with consecutive rapid solidification) by the laser device, allowing the power terminal to be connected to the substrate.

A method to connect power terminals to substrates within semiconductor packages is disclosed. The power terminal connection method minimally adapts the power terminal so that laser treatment can be used to connect the power terminal to the substrate. The power terminal may be adapted in a variety of ways, such that an interface between the power terminal and the substrate may be transformed (melted with consecutive rapid solidification) by the laser device, allowing the power terminal to be connected to the substrate.

A power conversion device is capable of achieving three requirements to restrict a surge voltage, ensure high radiation performance of SW elements, and restrict ringing at the same time. In a power conversion device, element modules of two SW elements are stacked in a thickness direction via an insulating layer in such a manner that lateral surfaces are aligned parallel to each other in a same orientation, and a positive terminal of one SW element and a negative terminal of the other SW element are disposed so as to overlap each other in the thickness direction.

One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.