An embodiment related to a package is disclosed. The package includes a component mounted to a die attach region on a package substrate. A passive component with first and second passive component terminals is vertically attached to the package substrate. An encapsulant is disposed over the package substrate to encapsulate the package. In one embodiment, an external component is stacked above the encapsulant and is electrically coupled to the encapsulated package.

A electronic multi-output device having a substrate including a pad and pins. A composite first chip has a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface. Patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. The second terminals are connected by discrete first and second metal clips to respective substrate pins. A composite second chip has a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to be vertically attached with its first terminals to the first and second clips, respectively. The third terminals are connected by discrete clips to respective substrate pins. The common second terminal is connected by a common clip to a substrate pin.

A package is disclosed. In one example, the package comprises a carrier, a first chip with an integrated transistor and comprising a first terminal attached on the carrier, a second terminal, and a third terminal, wherein the first terminal and the third terminal are formed on one main surface of the first chip and the second terminal is formed on an opposing other main surface of the first chip. A conductive structure is attached on the second terminal, an encapsulant is at least partially encapsulating the carrier, the first chip, and the conductive structure, and an insulating layer is arranged on a surface portion of the conductive structure or of the carrier. The surface portion is exposed beyond the encapsulant.

A semiconductor package is configured for electrically connecting an external component to a top surface of the semiconductor package. The semiconductor package includes a raised connector that extends from a lead frame portion, vertically through encapsulation material, and is exposed at the top surface. A semiconductor component is electrically connected to the lead frame portion. The raised connector includes a vertical column and a horizontal pad, contiguous with each other. The raised connector has a continuous core, which is electrically conductive, extending throughout the vertical column and throughout the horizontal pad. The vertical column is attached to the lead frame portion. A top surface of the horizontal pad is exposed at a top surface of the encapsulation material. The raised connector may include two or more vertical columns. The semiconductor package may include two or more raised connectors, each attached to the lead frame portion.

A semiconductor package and a method of manufacturing the same are provided, in which a height and a one-dimensional area of the semiconductor package may be reduced. The semiconductor package includes a package substrate, a chip stack structure including at least two semiconductor chips aligned with one another and stacked on the package substrate in a vertical direction, each of the at least two semiconductor chips including chip pads exposed at a side surface thereof, an anisotropic conductive film (ACF) covering a side surface of the chip stack structure, and a conductive pattern film covering the ACF and including a conductive pattern connecting the chip pads to a substrate pad of the package substrate.

A method of manufacturing a device package. The method comprises patterning a first substrate to form patterned regions comprising a thermal oxide layer. The method further comprises directly bonding the patterned regions of the first substrate to a second substrate to form a bonding interface. The bonded first and second substrates form an integrated cooling assembly comprising a coolant chamber volume. Portions of the first substrate exposed to the coolant chamber volume comprise a native oxide layer.

In examples, semiconductor package comprises a semiconductor die having a device side including circuitry; a sensor on the device side; a metal ring on the device side to at least partially define a cavity vertically aligned with the sensor, with the metal ring having a top metal ring surface facing away from the semiconductor die and an exterior metal ring surface facing away from the sensor; and a metal pillar on the device side and having a top metal pillar surface facing away from the semiconductor die. The package also comprises a tie bar extending approximately parallel to the device side of the semiconductor die and coupled with solder to the top metal ring surface, with the tie bar exposed to a first exterior surface of the package. The package comprises a conductive member including a conductive terminal exposed to a second exterior surface of the package, a vertical member coupled to the conductive terminal and extending toward the first exterior surface of the package, and a horizontal member coupled to the vertical member, with the horizontal member soldered to the top metal pillar surface. The package comprises a mold compound contacting the exterior metal ring surface, with the mold compound absent from the cavity.

In a general aspect, a semiconductor device assembly includes a substrate having a patterned metal layer disposed thereon, a first semiconductor die, the first semiconductor die disposed on a first portion of the patterned metal layer, and a second semiconductor die disposed on the first portion of the patterned metal layer. The assembly also includes a first electrical connection electrically coupling a second portion of the patterned metal layer with the first semiconductor die. and a second electrical connection electrically coupling the second portion of the patterned metal layer with the second semiconductor die. The second electrical connection is substantially electrically balanced with the first electrical connection.

Provided is a clip structure for a semiconductor package comprising: a first bonding unit bonded to a terminal part of an upper surface or a lower surface of a semiconductor device by using a conductive adhesive interposed therebetween, a main connecting unit which is extended and bent from the first bonding unit, a second bonding unit having an upper surface higher than the upper surface of the first bonding unit, an elastic unit elastically connected between the main connecting unit and one end of the second bonding unit, and a supporting unit bent and extended from the other end of the second bonding unit toward the main connecting unit, wherein the supporting unit is formed to incline at an angle of 1 through 179 from an extended surface of the main connecting unit and has an elastic structure so that push-stress applying to the semiconductor device while molding may be dispersed.

A stack includes a first power semiconductor device in a first chip and a second power semiconductor device in a second chip. The first power semiconductor device is configured for active operation during which an application load current is conducted by the first power semiconductor device and power losses occur in the first power semiconductor device. The second power semiconductor device is configured for passive operation during which a voltage is blocked. The stack further includes a heat sink interface configured to dissipate the power losses. The second chip is arranged between the first chip and the heat sink interface.