An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

The present disclosure relates to extremely high frequency (“EHF”) systems and methods for the use thereof, and more particularly to board-to-board connections using contactless connectors.

In one implementation, a semiconductor package includes an integrated circuit (IC) attached to a die paddle segment of a first patterned conduct carrier and coupled to a switch node segment of the first patterned conductive carrier by an electrical connector. In addition, the semiconductor package includes a second patterned conductive carrier situated over the IC, a magnetic material situated over the second patterned conductive carrier, and a third patterned conductive carrier situated over the magnetic material. The second patterned conductive carrier and the third patterned conductive carrier are electrically coupled so as to form windings of an integrated inductor in the semiconductor package.

A semiconductor device includes a die pad, a semiconductor element, a joining layer, a first conductive member, and a second conductive member. The semiconductor element has a first electrode opposing an obverse surface of the die pad, and a second electrode and a third electrode that are opposite to the first electrode in a thickness direction. The first electrode is electrically joined to the obverse surface. The joining layer electrically joins the first electrode and the obverse surface to each other. The first conductive member is electrically joined to the second electrode. The second conductive member is electrically joined to the third electrode. The area of the third electrode is smaller than the area of the second electrode as viewed along the thickness direction. The Young's modulus of the second conductive member is smaller than the Young's modulus of the first conductive member.

A semiconductor package is disclosed. The package includes a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die region. A die having first and second major die surfaces is attached onto the die region. The second major die surface is attached to the die region. The first major die surface includes a sensor region and a cover adhesive region surrounding the sensor region. The package also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the sensor region. The protective cover includes a recessed structure on the second major cover surface. The recessed structure is located above die bond pads on the die to create an elevated space over peak portions of wire bonds on the die bond pads. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed.

Disclosed are a semiconductor device and a stacked semiconductor package. The semiconductor device may include a semiconductor chip and a plurality of chip pads disposed on the semiconductor chip in a second horizontal direction perpendicular to a first horizontal direction. The plurality of chip pads may include: a first chip pad connected to a wire extending in the first horizontal direction, when seen from the top; and a second chip pad connected to a diagonal wire extending in a direction at an angle to the first and second horizontal directions, when seen from the top. The width of the first chip pad in the second horizontal direction may be smaller than the width of the second chip pad in the second horizontal direction.

A leadframe includes a peripheral frame, a plurality of lead pads, and a die attach pad (DAP). Each lead pad is physically connected to the peripheral frame by a respective connecting portion. The DAP is surrounded by the plurality of lead pads. The DAP includes a first protruding portion coupled to a first lead pad on a first side of the DAP and a second protruding portion coupled to a second lead pad on a second side of the DAP opposite the first side. The DAP does not comprise direct connections to the peripheral frame. The leadframe further includes two or more of the lead pads disposed on either side of the first lead pad on the first side of the DAP; and two or more of the lead pads disposed on either side of the second lead pad on the second side of the DAP.

A semiconductor package includes first bump structures that include a stud portion disposed below the second rear surface pads of the first group, and a bonding wire portion that extends from the stud portion and is connected to the first front surface pads of the first group; second bump structures disposed below the second rear surface pads of the second group; an encapsulant that encapsulates the second semiconductor chip and the first and second bump structures; and a redistribution structure disposed below the encapsulant, and that includes an insulating layer, redistribution layers disposed below the insulating layer, and redistribution vias that penetrate through the insulating layer and connect the redistribution layers to the first bump structures or the second bump structures. At least a portion of the redistribution vias connected to the first bump structures is in contact with the stud portion.

In examples, a semiconductor package comprises a first driver die adapted to be coupled to a high-side switch of a power supply, the first driver die adapted to drive a gate of the high-side switch. The package also includes a second driver die adapted to be coupled to a low-side switch of the power supply, the second driver die adapted to drive a gate of the low-side switch. The package also includes a controller die positioned between the first and second driver dies and configured to control the first and second driver dies. The package also includes a pair of bond wires configured to provide a differential signal between the controller die and the first driver die, a vertical plane of a bond wire in the pair of bond wires and a vertical plane of a side surface of the first driver die having an angle therebetween ranging from 80 to 95 degrees.

A semiconductor device includes a switching element, a control element that controls the switching element, an island lead on which the switching element and the control element are mounted, and a plurality of terminal leads. The switching element includes a first electrode, a second electrode and a third electrode, where the first electrode and the second electrode are offset from the third electrode in a first sense of a thickness direction. The island lead has an obverse surface facing in the first sense of the thickness direction and supporting the switching element and the control element. Each terminal lead is electrically connected to the second electrode or the control element. The island lead is spaced apart from the plurality of terminal leads.