In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

A module includes an electronic component, an enclosure at least partially enclosing the electronic component and defining a module interface at which the module is configured to be mounted on a mounting base, and a gas flow-inhibiting sealing at the module interface and configured to inhibit gas from propagating from an exterior of the module towards the electronic component. An electronic device that includes the module and a method of manufacturing the module are also described.

A semiconductor device includes a transistor die having top and bottom die surfaces, an electrically conductive structure, and input and output pads formed at the top die surface. An isolation structure is interposed between the input and output pads of the transistor die. The isolation structure extends above the top die surface, is coupled to the conductive structure, and is connected to a common return path of the transistor die. The isolation structure may be formed from one or more bondwires and is configured to reduce mutual coupling between input and output interconnects of the semiconductor device.

A semiconductor device includes a transistor die having top and bottom die surfaces, an electrically conductive structure, and input and output pads formed at the top die surface. An isolation structure is interposed between the input and output pads of the transistor die. The isolation structure extends above the top die surface, is coupled to the conductive structure, and is connected to a common return path of the transistor die. The isolation structure may be formed from one or more bondwires and is configured to reduce mutual coupling between input and output interconnects of the semiconductor device.

A semiconductor die includes a semiconductor body having first and second active portions. The first active portion includes first source regions. The second active portion includes second source regions. A gate structure extends from a first surface into the semiconductor body and has a longitudinal gate extension along a lateral first direction. A first load pad and the first source regions are electrically connected. A second load pad and the second source regions are electrically connected. A gap laterally separates the first and second load pads. A lateral longitudinal extension of the gap is parallel to the first direction or deviates therefrom by not more than 60 degree. A connection structure electrically connects the first and second load pads. The connection structure is formed in a groove extending from the first surface into the semiconductor body and/or in a wiring layer formed on the first surface.

An electric device with terminal notches includes a main body, a plurality of SMT leads and a plurality of plating layers. Each of the SMT leads is extended from the main body and ended up with a lead end surface furnished with a terminal notch, where the terminal notch has a notch peripheral surface. Each of the plating layers covers at least the notch peripheral surface of the corresponding SMT lead. In addition, a method for manufacturing the same electric device with terminal notches is also provided.

A semiconductor package encapsulant is enclosed. In one example, the semiconductor package encapsulant is for at least partially encapsulating a semiconductor component, wherein the semiconductor package encapsulant comprises metal activated inorganic filler particles providing a corrosion protection function.

A semiconductor device includes a semiconductor element having a surface electrode layer; a first wire that is electrically connected to the first main surface of the surface electrode layer at a plurality of first connecting portions and is arranged in a first direction on the first main surface; and a second wire that is electrically connected to the first main surface of the surface electrode layer at a second connecting portion and is arranged in a second direction on the first main surface, wherein a second circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the second wire, is larger than a first circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the first wire.

In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

A display device includes: an array substrate including a display area, of an image, including a plurality of pixels arranged in an array; a first circuit that is disposed at the array substrate to face an end of the display area, and controls drive of the plurality of pixels; and a second circuit that controls drive of the first circuit. The first circuit includes a plurality of first terminals arranged on the array substrate. The first circuit includes a plurality of second terminals each connected by at least one wire bond to a corresponding one of a plurality of terminals included in the second circuit.