A variety of applications can include systems with packaged electronic devices having multiple dies arranged on a substrate with a downset design. A substrate with a downset design can include an upper portion and a lower portion with a downset portion connecting the upper portion to the lower portion. The downset portion can include through vias to provide conductive paths between the lower portion and the upper portion. Dies can be positioned with a region defined by walls of the downset portion with a non-conductive film covering the dies in the region defined by walls of the downset portion. Additional dies can be positioned on the non-conductive film and the upper portion of the substrate. A packaged electronic device having a substrate with a downset design can be implemented to raise the neutral axis of the packaged electronic device to near the top surface of the dies.

A power electronic arrangement having a power semiconductor module and an external load-connecting element is provided with the external load-connecting element has a first connection device, and the power semiconductor module has a housing, a base plate and an internal load-connecting element with a second connection device, wherein the base plate has a first cut out through which the first connection device extends into the interior of the power semiconductor module and is connected there in a frictionally locking and electrically conductive fashion to a second connection device of the internal load-connecting element.

A semiconductor device includes a gate interconnect, extending in a first direction, and configured to transmit an input signal, and a transistor including gate electrodes extending in a second direction perpendicular to the first direction, and spaced apart from one another, and connected to the gate interconnect, and source and drain regions alternately arranged along the first direction, so that each gate electrode is sandwiched between the source and drain region which are adjacent to each other. The semiconductor device also includes drain interconnects, arranged above the drain regions, and connected to the drain regions, respectively, an output interconnect, connected to the drain interconnects, and configured to transmit an output signal output from the drain regions, and stubs connected to the drain interconnects, respectively. At least one of the stubs is connected to one of the drain interconnects at an end opposite from the gate interconnect.

A semiconductor module includes a sealing body including a terminal portion electrically connected to a semiconductor element and an insulating resin that seals the semiconductor element, a case that houses the sealing body, and a conductive member provided in the case and including a contact portion that has contact with the terminal portion of the sealing body. The terminal portion is exposed from the insulating resin. The case includes a holding member attaching portion capable of attaching a holding member used in combination with the case and holds the sealing body in a state where the terminal portion of the sealing body has contact with the contact portion of the conductive member. The holding member attaching portion is configured so that a pressing load is applied to a contact surface of the contact portion contacting the terminal portion when the holding member is attached.

A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.

An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.

A semiconductor apparatus includes (i) semiconductor chips including a power semiconductor chip including a switch and a control semiconductor chip including a control circuit configured to control the switch, (ii) redistribution layers including a first redistribution layer that electrically connects a first semiconductor chip to a second semiconductor chip from among the semiconductor chips, (iii) a first sealing material that seals the semiconductor chips and the redistribution layers, (iv) an insulating substrate including a first conductor layer, a second conductor layer and an insulating layer between the first and second conductor layers, in which the insulating substrate is fixed to the first sealing material to be opposed to the semiconductor chips and the redistribution layers, and (v) a second sealing material that seals the insulating substrate and the first sealing material.

A leadframe includes a die pad having a surface that includes a region for mounting a semiconductor chip, and a flat film and a roughened film on the surface of the die pad. In a plan view, the flat film is along and outside the outer edge of the region and the roughened film is inside and outside the flat film. The roughened film includes a roughened plating film and a plating film on the roughened plating film. The plating film follows the shape of the roughened plating film to have a roughened surface. The flat film has a flatter surface than the roughened film, and includes a first metal film formed of the same material as the roughened plating film and a second metal film on the first metal film. The second metal film is an alloy film including metals of the roughened plating film and the plating film.

An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The plurality of metal layers have a topmost metal layer disposed furthest away from the substrate and a first interconnect metal layer formed nearest to the substrate. The first interconnect metal layer is disposed at a first distance away from the substrate, whereas the topmost metal layer is disposed at an isolation distance away from a first adjacent metal layer formed nearest to the topmost metal layer. A portion of the topmost metal layer forms a first plate. The first plate is configured to transmit the first signal from the first circuit to a second plate that is connected to the second circuit, but electrically isolated from the first plate.

A power electronics module having a base plate, a circuit carrier arranged on the base plate and a plurality of conductor tracks which are electrically insulated from the base plate. A power semiconductor component is arranged on one of the conductor tracks, and has a load connection element. In this case, the base plate has a substantially continuous first recess and the circuit carrier has a substantially continuous second recess, wherein the first and second recesses are arranged such that they are in alignment with one another. The load connection element has a first contact device which is in electrically conductive contact with a contact area of that side of the conductor track which is averted from the base plate, a second contact device for externally making contact with the circuit carrier, and a connecting section, which extends through the first and second recesses, between the first and second contact devices.