A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. Memory devices can be formed on a first wafer. First metal pads can be formed on the first wafer and coupled to the memory devices. The memory devices can be tested via the first metal pads. The first metal pads can be removed from the first wafer. Subsequently, second metal pads on the first wafer can be bonded, via a wafer-on-wafer bonding process, to third metal pads on a second wafer. Each memory device on the first wafer can be aligned with and coupled to a respective logic device on the second wafer.

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

An electronics assembly includes a semiconductor device having a first device surface and at least one device conductive layer disposed directly thereon. A cooling structure coupled to the semiconductor device includes a manifold layer, a microchannel layer bonded to the manifold layer, at least one planar side cooling structure, and one or more cooling structure conductive layers. The manifold layer includes a fluid inlet and a fluid outlet and defines a first cooling structure surface. The microchannel layer comprises at least one microchannel fluidly coupled to the fluid inlet and the fluid outlet and defines a second cooling structure surface opposite from the first cooling structure surface. The planar side cooling structure surface is transverse to the first and the second cooling structure surfaces. The cooling structure conductive layers are disposed directly on the first cooling structure surface, the second cooling structure surface, and the planar side cooling structure surface.

A semiconductor module is configured to convert a direct current to a three-phase alternating current, and to supply the three-phase alternating current to a three-phase motor to drive the three-phase motor, wherein the first to the third control signal terminals Q1, Q2, and Q3 are arranged in a direction along which the first side B1 extends in a manner that one ends of the first to the third control signal terminals are in the vicinity of the first side B1 of the substrate B, and wherein the fourth to the sixth control signal terminals Q4, Q5, and Q6 are arranged in a direction along which the second side B2 extends in a manner that one ends of the fourth to the sixth control signal terminals are in the vicinity of the second side B2 of the substrate B.

A semiconductor module is configured to convert a direct current to a three-phase alternating current, and to supply the three-phase alternating current to a three-phase motor to drive the three-phase motor, wherein the first to the third control signal terminals Q1, Q2, and Q3 are arranged in a direction along which the first side B1 extends in a manner that one ends of the first to the third control signal terminals are in the vicinity of the first side B1 of the substrate B, and wherein the fourth to the sixth control signal terminals Q4, Q5, and Q6 are arranged in a direction along which the second side B2 extends in a manner that one ends of the fourth to the sixth control signal terminals are in the vicinity of the second side B2 of the substrate B.

Provided are a semiconductor device having a stress alleviation structure in which resistance to stress concentrated on a predetermined portion of the semiconductor device is improved, and a method for manufacturing the semiconductor device. The semiconductor device includes: a first dielectric layer; a seed layer having a first land portion formed on the first dielectric layer; a second land portion formed on the seed layer and having a diameter larger than a diameter of the first land portion that can be connected to the wiring pattern; an external terminal formed on the second land portion; and a second dielectric layer covering the seed layer, the first land portion, and the second land portion.

A chip package for optical sensing includes a substrate, and a semiconductor device positioned on the substrate and coupled to the substrate through a first conducting element. Two molding processes are applied, to form a first colloid body on the substrate so as to cover the semiconductor device and, on the first colloid body, to form a second colloid body which covers an optical device. The optical device is electrically connected to the substrate through a second conducting element. The light transmittance of the second colloid body exceeds that of the first colloid body.

A chip package for optical sensing includes a substrate, and a semiconductor device positioned on the substrate and coupled to the substrate through a first conducting element. Two molding processes are applied, to form a first colloid body on the substrate so as to cover the semiconductor device and, on the first colloid body, to form a second colloid body which covers an optical device. The optical device is electrically connected to the substrate through a second conducting element. The light transmittance of the second colloid body exceeds that of the first colloid body.