The present disclosure is directed to a hybrid conductive ink including: silver nanoparticles and eutectic low melting point alloy particles, wherein a weight ratio of the eutectic low melting point alloy particles and the silver nanoparticles ranges from 1:20 to 1:5. Also provided herein are methods of forming an interconnect including a) depositing a hybrid conductive ink on a conductive element positioned on a substrate, wherein the hybrid conductive ink comprises silver nanoparticles and eutectic low melting point alloy particles, the eutectic low melting point alloy particles and the silver nanoparticles being in a weight ratio from about 1:20 to about 1:5; b) placing an electronic component onto the hybrid conductive ink; c) heating the substrate, conductive element, hybrid conductive ink and electronic component to a temperature sufficient i) to anneal the silver nanoparticles in the hybrid conductive ink and ii) to melt the low melting point eutectic alloy particles, wherein the melted low melting point eutectic alloy flows to occupy spaces between the annealed silver nanoparticles, d) allowing the melted low melting point eutectic alloy of the hybrid conductive ink to harden and fuse to the electronic component and the conductive element, thereby forming an interconnect. Electrical circuits including conductive traces and, optionally, interconnects formed with the hybrid conductive ink are also provided.

A semiconductor substrate includes a dielectric insulation layer and a structured metallization layer having at least five separate sections attached to the dielectric insulation layer, a first switching element having first emitter and collector terminals, a second switching element having second emitter and collector terminals, a first diode element having first anode and cathode terminals, and a second diode element having second anode and cathode terminals. The switching and diode elements are arranged on a first section of the metallization layer, with the collector and cathode terminals electrically coupled to the first section. The first anode and emitter terminals are electrically coupled to second and third sections. The second anode and emitter terminals are electrically coupled to fourth and fifth sections. The first section separates the second and fourth adjacent sections from the third and fifth adjacent sections.

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

A power module (1) includes a group of at least three rectangular electrical power components (11, 12, 13, 14, 23, 24, 25, 26) arranged on a substrate (2), wherein in that at least one side (31) of at least one of the rectangular electrical power components (11, 14) is not orthogonal or parallel to a line (3) that passes through the geometric centres of the remaining rectangular electrical power components (12, 13) of the group.

A semiconductor device includes a metal base plate, a case component, and a metal component. The metal component is fixed to the case component. A partial region of the metal component is exposed from the case component. The partial region is bonded to the base plate in a bonding portion. In the bonding portion, a surface of the partial region and a surface of the base plate are in direct contact with each other and integrated.

A package structure includes a metal member and a resin member. The metal member has an obverse surface facing one side in a first direction. The resin member is disposed in contact with at least a portion of the obverse surface. The obverse surface has a roughened area. The roughened area includes a plurality of first trenches recessed from the obverse surface, each of the first trenches having a surface with a greater roughness than the obverse surface. The plurality of first trenches extend in a second direction perpendicular to the first direction and are next to each other in a third direction perpendicular to the first direction and the second direction. The plurality of first trenches are filled up with the resin member.

An electronic element mounting substrate includes a substrate including a first layer, a second layer located on a lower surface of the first layer, and a third layer located on a lower surface of the second layer, and on which an electronic element is to be mounted. The substrate has a via conductor that passes through the first layer to the third layer in a vertical direction. The substrate includes respective electrical conductor layers located between the respective layers and connected to the via conductor in a plan perspective. Each electrical conductor layer includes a land portion surrounding the via conductor, a clearance portion surrounding the land portion, and a peripheral portion surrounding the clearance portion and electrically insulated from the land portion with the clearance portion interposed between the land portion and the peripheral portion. The first land portion has, in a plan perspective, a first portion overlapping the second land portion, and the first clearance portion has, in a plan perspective, a second portion not overlapping the second clearance portion. The first peripheral portion and the second peripheral portion each have, in a vertical cross-sectional view, an end portion that becomes thinner as a distance from the via conductor increases.

A semiconductor device includes a semiconductor portion with a first surface at a front side, wherein the semiconductor portion includes an active area, a termination structure laterally surrounding the active area, and a field-free region between the termination structure and a lateral outer surface of the semiconductor portion. The field-free region includes a probe contact region and a main portion. The probe contact region and the main portion form a semiconductor junction. A probe pad on the first surface and the probe contact region form an ohmic contact. A protection passivation layer on the first surface is formed on at least the termination structure and exposes the probe pad.

A semiconductor device includes a semiconductor element, a lead frame, a conductive member, a resin composition and a sealing resin. The semiconductor element has an element front surface and an element back surface facing away in a first direction. The semiconductor element is mounted on the lead frame. The conductive member is bonded to the lead frame, electrically connecting the semiconductor element and the lead frame. The resin composition covers a bonded region where the conductive member and lead frame are bonded while exposing part of the element front surface. The sealing resin covers part of the leadframe, the semiconductor element, and the resin composition. The resin composition has a greater bonding strength with the lead frame than a bonding strength between the sealing resin and lead frame and a greater bonding strength with the conductive member than a bonding strength between the sealing resin and conductive member.

A bonded structure includes a semiconductor element, an electrical conductor and a sintered metal layer. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a first direction and includes a reverse-surface electrode on the element reverse surface. The electrical conductor has a mount surface facing in a same direction as the element obverse surface and supports the semiconductor element with the mount surface facing the element reverse surface. The sintered metal layer bonds the semiconductor element to the electrical conductor and electrically connects the reverse-surface electrode and the electrical conductor. The mount surface includes a roughened area roughened by a roughening process. The sintered metal layer is formed on the roughened area.