A semiconductor device includes a semiconductor chip having a device forming surface on which a device structure is formed, a first conductive layer formed on the device forming surface of the semiconductor chip, a second conductive layer formed on the first conductive layer, a first wire that is connected to the second conductive layer and that is made of a material composed mainly of copper, and a third conductive layer that is formed between the first conductive layer and the second conductive layer and that includes a material harder than copper.

A semiconductor device, having a substrate including an insulating plate and a circuit board provided on a front surface of the insulating plate. The circuit board has a first disposition area and a second disposition area with a gap therebetween, and a groove portion, of which a longitudinal direction is parallel to the gap, formed in the gap. The semiconductor device further includes a first semiconductor chip and a second semiconductor chip located on the circuit board in the first disposition area and the second disposition area, respectively, and a blocking member located in the gap across the groove portion in parallel to the longitudinal direction in a plan view of the semiconductor device.

A semiconductor device includes a case enclosing a region filled with a sealing material. The case is made of resin. An electrode is fixed to the case. A section, which is a part of the electrode, is provided with a cutout that allows a part of the resin making the case to be exposed to the region.

An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a III-V semiconductor substrate, a first RF signal input terminal, a first RF signal output terminal, and a transistor (e.g., a GaN FET). The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.

A power module including at least one substrate, a housing arranged on the at least one power substrate, a first terminal electrically connected to the at least one power substrate, a second terminal including a contact surface, a third terminal electrically connected to the at least one power substrate, a plurality of power devices arranged on and connected to the at least one power substrate, and the third terminal being electrically connected to at least one of the plurality of power devices. The power module further including a base plate and a plurality of pin fins arranged on the base plate and the plurality of pin fins configured to provide direct cooling for the power module.

Evaluation board (EVB) assemblies or stacks utilized in tuning electronic modules are disclosed, as are methods for tuning such modules. In embodiments, the module testing assembly includes an EVB and an EVB baseplate. The EVB includes, in turn, an EVB through-port extending from a first EVB side to a second, opposing EVB side; and a module mount region on the first EVB side and extending about a periphery of the EVB through-port. The module mount region is shaped and sized to accommodate installation of a sample electronic module provided in a partially-completed, pre-encapsulated state fabricated in accordance with a separate thermal path electronic module design. A baseplate through-port combines with the EVB through-port to form a tuning access tunnel providing physical access to circuit components of the sample electronic module through the EVB baseplate from the second EVB side when the sample electronic module is installed on the module mount region.

An object is to provide a technique capable of improving the power efficiency of a semiconductor device. The semiconductor device includes first to sixth parallel connection bodies, each including a semiconductor switching element and a diode connected in antiparallel to the semiconductor switching element. At least one of the voltage drops of the second parallel connection body and the third parallel connection body is smaller than a voltage drop of at least one of the first parallel connection body, the fourth parallel connection body, the fifth parallel connection body, and the sixth parallel connection body.

A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.

A semiconductor device includes: a conductive base substrate; a semiconductor chip mounted on the base substrate and having a signal pad; a frame configured to surround the semiconductor chip, to be mounted on the base substrate, and to include a step having an inner first upper surface and an outer second upper surface higher than the first upper surface in a plan view, wherein a first conductor pattern provided on the first upper surface is electrically connected to the base substrate; a capacitive component mounted on the first conductor pattern; a signal terminal mounted on the second upper surface of the frame; a first bonding wire configured to electrically connect the signal pad and an upper surface of the capacitive component; and a second bonding wire configured to electrically connect the upper surface of the capacitive component and the signal terminal.

A semiconductor device includes a semiconductor element, a lead frame, a conductive member, a resin composition and a sealing resin. The semiconductor element has an element front surface and an element back surface facing away in a first direction. The semiconductor element is mounted on the lead frame. The conductive member is bonded to the lead frame, electrically connecting the semiconductor element and the lead frame. The resin composition covers a bonded region where the conductive member and lead frame are bonded while exposing part of the element front surface. The sealing resin covers part of the lead frame, the semiconductor element, and the resin composition. The resin composition has a greater bonding strength with the lead frame than a bonding strength between the sealing resin and lead frame and a greater bonding strength with the conductive member than a bonding strength between the sealing resin and conductive member.