A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a first side surface located on one side of a first direction, a second side surface located on the other side of the first direction, and third and fourth side surfaces that are separated from each other in a second direction orthogonal to both a thickness direction and the first direction and are connected to the first and second side surfaces. A first gate mark having a surface roughness larger than the other regions of the third side surface is formed on the third side surface. When viewed along the second direction, the first gate mark overlaps a pad gap provided between the first die pad and the second die pad in the first direction.

A package with a laminate substrate is disclosed. The laminate substrate includes a first layer with a first terminal and a second terminal. The laminate substrate also includes a second layer with a conductive element. The laminate substrate further includes a first via and a second via that electrically connect the first terminal to the conductive element and the second terminal to the conductive element, respectively. The package can include a die mounted on and electrically connected to the laminate substrate.

In examples, a semiconductor package comprises a first driver die adapted to be coupled to a high-side switch of a power supply, the first driver die adapted to drive a gate of the high-side switch. The package also includes a second driver die adapted to be coupled to a low-side switch of the power supply, the second driver die adapted to drive a gate of the low-side switch. The package also includes a controller die positioned between the first and second driver dies and configured to control the first and second driver dies. The package also includes a pair of bond wires configured to provide a differential signal between the controller die and the first driver die, a vertical plane of a bond wire in the pair of bond wires and a vertical plane of a side surface of the first driver die having an angle therebetween ranging from 80 to 95 degrees.

In some embodiments, a radio-frequency device can be manufactured by a method that includes forming or providing a substrate, fabricating or providing a flip chip die having a front side and a back side, and including an integrated circuit implemented on the front side, and mounting the front side of the flip chip die on the substrate. The method can further include implementing a shielding component over the back side of the flip chip die to provide electromagnetic shielding between a first region within or on the flip chip die and a second region away from the flip chip die.

In some embodiments, a radio-frequency device can be manufactured by a method that includes forming or providing a substrate, fabricating or providing a flip chip die having a front side and a back side, and including an integrated circuit implemented on the front side, and mounting the front side of the flip chip die on the substrate. The method can further include implementing a shielding component over the back side of the flip chip die to provide electromagnetic shielding between a first region within or on the flip chip die and a second region away from the flip chip die.

A transistor device includes a semiconductor substrate having a first major surface and transistor cells formed therein. Each transistor cell includes a drift region of a first conductivity type, a body region of an opposing second conductivity type arranged on the drift region, a source region of the first conductivity type arranged on the body region, a columnar field plate trench extending into the first major surface and including a field plate, and a gate trench structure extending into the first major surface and including a gate electrode. A first metallization structure on the first major surface provides a first contact pad for wire bonding. At least one of depth and doping level of the body region is locally increased within the transistor cells located within one or more first areas of the first major surface. One or more of the first areas are located underneath the first contact pad.

A transistor device includes a semiconductor substrate having a first major surface and transistor cells formed therein. Each transistor cell includes a drift region of a first conductivity type, a body region of an opposing second conductivity type arranged on the drift region, a source region of the first conductivity type arranged on the body region, a columnar field plate trench extending into the first major surface and including a field plate, and a gate trench structure extending into the first major surface and including a gate electrode. A first metallization structure on the first major surface provides a first contact pad for wire bonding. At least one of depth and doping level of the body region is locally increased within the transistor cells located within one or more first areas of the first major surface. One or more of the first areas are located underneath the first contact pad.

A semiconductor device includes: a first semiconductor chip mounted on a chip mounting portion via a first bonding material; and a second semiconductor chip mounted on the first semiconductor chip. Here, the first semiconductor chip has: a protective film located in an uppermost layer; and a first pad electrode exposed from the protective film at an inside of a first opening portion of the protective film. Also, the second semiconductor chip is mounted on a conductive material, which is arranged on the first pad electrode of the first semiconductor chip, via a second bonding material of an insulative property.

A WBGA package and a method of manufacturing a WBGA package are provided. The WBGA package includes a carrier having a first surface and a second surface opposite to the first surface of the carrier. The carrier has a through hole filled with a first package body and extending between the first surface and the second surface of the carrier. The WBGA package also includes an electronic component disposed on the second surface of the carrier. The electronic component includes a first bonding pad and a second bonding pad. The WBGA package also includes a first bonding wire electrically connected between the first bonding pad and the second bonding pad.

A semiconductor package having a package substrate including an upper surface, a controller, a first die stack, and a second die stack. The controller, the first die stack, and the second die stack are at the upper surface. The first die stack includes a first shingled sub-stack and a first reverse-shingled sub-stack. The first die stack also includes a first bridging chip between the first shingled and reverse-shingled sub-stacks. The second die stack similarly includes a second shingled sub-stack and a second reverse-shingled sub-stack. The second die stack also includes a second bridging chip bonded to the top of the second reverse-shingled sub-stack. At least a portion of a bottom semiconductor die of the first reverse-shingled sub-stack is vertically aligned with a semiconductor die of the second shingled sub-stack and a semiconductor die of the second reverse-shingled sub-stack.