A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.

The present disclosure relates to electric motors. The teachings thereof may be embodied in a power module, e.g., a power module for the delivery of a phase current for a current phase of an electric motor. For example, a power module may include: a circuit carrier having a surface; at least two first contact surfaces, a second contact surface, at least two third contact surfaces defined on the surface; a first power transistor connected to each of the at least two first contact surfaces; at least two second power transistors connected to the second contact surface; wherein the at least two second power transistors are connected via a further contact surface to one of the at least two third contact surfaces; and the at least two first and the at least two third contact surfaces are arranged one after the other, in one direction, and the second contact surface is disposed next to both the at least two first and the at least two third contact surfaces.

A semiconductor assembly includes a first FET integrated within the semiconductor assembly and comprising gate, source and drain terminals. The semiconductor assembly further includes a low voltage switching device integrated within the semiconductor assembly and being configured to electrically short a gate-source capacitance of the first FET responsive to a control signal.

An integrated circuit (IC) package with stacked die wire bond connections has two stacked IC dies, where a first die couples to a metallization structure directly and a second die stacked on top of the first die connects to the metallization structure through wire bond connections. The IC dies are coupled to one another through an interior metal layer of the metallization structure. Vias are used to couple to the interior metal layer.

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor chip having a first main surface including an active region and a peripheral region surrounding the active region; a first trench formed in the active region; a first insulating film formed on an inner surface of the first trench; a first electrode formed in the first trench interfacing the first insulating film, and forming a channel in a portion of the semiconductor chip facing the first insulating film; a second trench formed in the peripheral region and having a width greater a width of the first trench; a second insulating film formed on an inner surface of the second trench; and a second electrode formed in the second trench interfacing the second insulating film and electrically coupled to the first electrode.

A power semiconductor module includes a main substrate and power semiconductor chips. Each power semiconductor chip is bonded to the main conductive layer with the first power electrode. A first group of the power semiconductor chips is connected in parallel via the second power electrodes and a second group of the power semiconductor chips is connected in parallel via the second power electrodes. The module also includes a first insulation layer and a first conductive layer overlying the first insulation layer as well as a second insulation layer and a second conductive layer overlying the second insulation layer. The first conductive layer provides a first gate conductor area and a first auxiliary emitter conductor area for the first group. The second conductive layer provides a second gate conductor area and a second auxiliary emitter conductor area for the second group.

A semiconductor device includes an upper switching element, a lower switching element, an upper capacitor, and a lower capacitor. The upper switching element is formed by a wide-gap semiconductor and includes a first upper terminal, a second upper terminal, and an upper control terminal. The lower switching element is formed by a wide-gap semiconductor and includes a first lower terminal, a second lower terminal, and a lower control terminal. The upper capacitor is provided between the first upper terminal and the upper control terminal separately from the upper switching element. The lower capacitor is provided between the first lower terminal and the lower control terminal separately from the lower switching element. The second upper terminal and the first lower terminal are electrically connected.

A semiconductor device includes a semiconductor chip having an electrode pad, a terminal having a terminal pad, and a bonding wire. The bonding wire includes a first end portion, a first bonded portion bonded to the electrode pad, a loop portion extending between the semiconductor chip and the terminal, and a second bonded portion bonded to the terminal pad. The second bonded portion is a wedge bonded portion comprising a second end portion of the bonding wire opposite to the first end portion. A length of the first bonded portion in the first direction is greater than a length of the second bonded portion in the first direction.

A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.

A semiconductor device includes a first conductive plate, a second conductive plate, first switching elements, second switching elements, a first supply terminal and a second supply terminal. The first and second conductive plates are spaced apart from each other in a first direction. The first switching elements are bonded to the first conductive plate, and are electrically connected to the second conductive plate. The second switching elements are bonded to the second conductive plate. The first supply terminal is bonded to the first conductive plate. The second supply terminal has a region that overlaps with the first supply terminal as viewed in a plan view. The second supply terminal is spaced apart from the first conductive plate and the first supply terminal in a thickness direction perpendicular to the first direction. The second supply terminal is electrically connected to the second switching elements.