The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10.sup.−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

The present disclosure provides a LED display device, which includes: a LED display substrate and a driving substrate opposite to each other, the LED display substrate includes: a base and a plurality of LED chips located on a side of the base distal to the driving substrate; the driving substrate includes: a PCB and a driving control element located on the PCB, and the driving control element is electrically coupled to the LED chips through a plurality of first signal wires for providing driving signals for the LED chips.

A semiconductor device includes: a first wiring layer having a first main surface facing a thickness direction; a second wiring layer having a second main surface facing the same side as the first main surface and located away from the first wiring layer; a first semiconductor element having a first main surface electrode and bonded to the first main surface; a second semiconductor element having a second main surface electrode and bonded to the second main surface; a first terminal electrically connected to the second main surface electrode; a first conductive member bonded to the first main surface electrode and the second main surface; and a second conductive member bonded to the second main surface electrode and the first terminal, wherein the first terminal is located away from the first wiring layer in the thickness direction, and the second conductive member overlaps the first wiring layer in the thickness direction.

A semiconductor device includes a first conductive plate, a second conductive plate, first switching elements, second switching elements, a first supply terminal and a second supply terminal. The first and second conductive plates are spaced apart from each other in a first direction. The first switching elements are bonded to the first conductive plate, and are electrically connected to the second conductive plate. The second switching elements are bonded to the second conductive plate. The first supply terminal is bonded to the first conductive plate. The second supply terminal has a region that overlaps with the first supply terminal as viewed in a plan view. The second supply terminal is spaced apart from the first conductive plate and the first supply terminal in a thickness direction perpendicular to the first direction. The second supply terminal is electrically connected to the second switching elements.

A semiconductor package includes a package substrate including: first and second bond finger arrays, each of the first and second finger arrays arranged in a first direction on a surface of the package substrate; a first semiconductor chip disposed on the surface of the package substrate and including a first chip pad array corresponding to the first bond finger array; a second semiconductor chip disposed on the surface of the package substrate and including a second chip pad array corresponding to the second bond finger array; first bonding wires connecting bond fingers of the first bond finger array to chip pads of the first chip pad array; and second bonding wires connecting bond fingers of the second bond finger array to chip pads of the second chip pad array.

In one example embodiment, a PCBA, an optoelectronic module, an electrical coupling, and/or a high speed interconnect may include a first contact pad, a second contact pad adjacent to and spaced apart from the first contact pad, a first wire coupled to the first contact pad via a first ball bump, and a second wire coupled to the second contact pad via a double ball bump.

A semiconductor package structure includes a vapor chamber, a plurality of electrical contacts, a semiconductor die and an encapsulant. The vapor chamber defines an enclosed chamber for accommodating a working liquid. The electrical contacts surround the vapor chamber. The semiconductor die is disposed on the vapor chamber, and electrically connected to the electrical contacts through a plurality of bonding wires. The encapsulant covers a portion of the vapor chamber, portions of the electrical contacts, the semiconductor die and the bonding wires.

A microelectronic package may include a substrate having first and second surfaces each extending in first and second directions, a NAND wafer having a memory storage array, a bitline driver chiplet configured to function as a bitline driver, and a wordline driver chiplet configured to function as a wordline driver. The NAND wafer may be coupled to the first surface of the substrate, and the bitline and wordline driver chiplets may each be mounted to a front surface of the NAND wafer. The NAND wafer may have element contacts electrically connected with conductive structure of the substrate. The bitline and wordline driver chiplets may be elongated along the first and second directions, respectively. Front surfaces of the bitline driver chiplet and the wordline driver chiplet may be arranged in a single common plane and may be entirely contained within an outer periphery of the front surface of the NAND wafer.

A semiconductor package includes a substrate, a semiconductor chip and a heat dissipation structure. The semiconductor chip includes a first surface, a second surface opposite to the first surface, and at least one chip pad disposed adjacent to the first surface. The chip pad is electrically connected to the substrate. The heat dissipation structure is disposed adjacent to the second surface of the semiconductor chip and a portion of the substrate. An area of the heat dissipation structure is greater than an area of the semiconductor chip.

According to the present disclosure, a semiconductor device includes a substrate, a semiconductor chip provided on the substrate, a case having a wall portion provided on the substrate and surrounding the semiconductor chip, and an overhang protruding from the wall portion toward an inside of a region surrounded by the wall portion and a resin that fills the region surrounded by the wall portion, wherein the overhang has an upper surface, and an inclined surface that is provided below the upper surface and on which a distance to the substrate decreases with an increase in distance from a tip of the overhang, the overhang being provided with a through hole penetrating from the inclined surface to the upper surface, and the through hole extends perpendicularly from the inclined surface.