A semiconductor-mounted product includes a semiconductor package, a wiring substrate, four or more soldered portions, and a resin-reinforced portion. Each of the soldered portions electrically connects the semiconductor package to the wiring of the wiring substrate. The resin-reinforced portion is formed on a side surface of each of the soldered portions. Each of the soldered portions has a first solder region formed closer to the semiconductor package than the wiring substrate and a second solder region formed closer to the wiring substrate than the semiconductor package. A proportion of a void present in a polygon connecting centers of soldered portions located at outermost positions among the soldered portions to a sum of the void and the resin-reinforced portion is from 10% to 99%, inclusive.

A display device includes an array substrate, two light-emitting element substrates, a plurality of first connection elements, and a plurality of second connection elements. The array substrate includes two pixel circuits. Each of the pixel circuits includes three sub-pixel circuits, three first conductive pads, and a second conductive pad. Each of the light-emitting element substrates includes three light-emitting elements, three first connection pads, and a second connection pad. The first connection elements respectively and electrically connect corresponding one of the first conductive pads to corresponding one of the first connection pads. The second connection elements respectively and electrically connect corresponding one of the second conductive pads to corresponding one of the second connection pads.

A display device includes an array substrate, two light-emitting element substrates, a plurality of first connection elements, and a plurality of second connection elements. The array substrate includes two pixel circuits. Each of the pixel circuits includes three sub-pixel circuits, three first conductive pads, and a second conductive pad. Each of the light-emitting element substrates includes three light-emitting elements, three first connection pads, and a second connection pad. The first connection elements respectively and electrically connect corresponding one of the first conductive pads to corresponding one of the first connection pads. The second connection elements respectively and electrically connect corresponding one of the second conductive pads to corresponding one of the second connection pads.

Provided is connection wiring capable of inhibiting connection defects between bumps and pads at the time of semiconductor chip mounting and also allowing an increase in the number of pads. In an area between a pad row in any stage and a pad row in an adjacent stage, a first line 31 is disposed so as to pass under an adjacent second line 32, or a second line 32 is disposed so as to pass over an adjacent first line 31. In this case, three lines are disposed in any area between pads 20 in each stage such that the three lines include a first line 31 situated in the middle, and second lines 32 are situated so as to have the first line 31 positioned therebetween. Thus, the pitch between the pads 20 can be further reduced without reducing the width of the pads 20.

Provided is connection wiring capable of inhibiting connection defects between bumps and pads at the time of semiconductor chip mounting and also allowing an increase in the number of pads. In an area between a pad row in any stage and a pad row in an adjacent stage, a first line 31 is disposed so as to pass under an adjacent second line 32, or a second line 32 is disposed so as to pass over an adjacent first line 31. In this case, three lines are disposed in any area between pads 20 in each stage such that the three lines include a first line 31 situated in the middle, and second lines 32 are situated so as to have the first line 31 positioned therebetween. Thus, the pitch between the pads 20 can be further reduced without reducing the width of the pads 20.

A mounting structure includes a bonding material (106) that bonds second electrodes (104) of a circuit board (105) and bumps (103) of a semiconductor package (101), the bonding material (106) being surrounded by a first reinforcing resin (107). Moreover, a portion between the outer periphery of the semiconductor package (101) and the circuit board (105) is covered with a second reinforcing resin (108). Even if the bonding material (106) is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained.

A mounting structure includes a bonding material (106) that bonds second electrodes (104) of a circuit board (105) and bumps (103) of a semiconductor package (101), the bonding material (106) being surrounded by a first reinforcing resin (107). Moreover, a portion between the outer periphery of the semiconductor package (101) and the circuit board (105) is covered with a second reinforcing resin (108). Even if the bonding material (106) is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained.

The method of bonding an interposer and an integrated circuit chip includes preparing an interposer including an insulator and conductive lines each having one end exposed to a first surface of the insulator and another end exposed to a second surface opposite to the first surface; placing a bonding mask on the interposer; forming through-holes on the bonding mask before or after the placing of the bonding mask on the interposer; filling the plurality with a conductive material; and bonding an integrated circuit chip to the bonding mask.

The method of bonding an interposer and an integrated circuit chip includes preparing an interposer including an insulator and conductive lines each having one end exposed to a first surface of the insulator and another end exposed to a second surface opposite to the first surface; placing a bonding mask on the interposer; forming through-holes on the bonding mask before or after the placing of the bonding mask on the interposer; filling the plurality with a conductive material; and bonding an integrated circuit chip to the bonding mask.

An apparatus includes a circuit substrate including a circuit trace and a micro-sized semiconductor device die electrically connected to the circuit substrate. The micro-sized semiconductor device die has a height not greater than 400 microns and a width not greater than 800 microns. An anisotropic conductive adhesive (ACA) is disposed between the circuit substrate and the micro-sized semiconductor device die, thereby providing an electrical connection from the circuit substrate to the micro-sized semiconductor device die.