A semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of the first substrate. A second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate with the first semiconductor component and second semiconductor component between the first substrate and second substrate. A first encapsulant is deposited between the first substrate and second substrate. A SiP submodule is disposed over the first substrate or second substrate opposite the encapsulant. A shielding layer is formed over the SiP submodule.

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

An electronic component package of an embodiment of the disclosure includes a base, a first plated layer, a first electronic component chip, a second plated layer, and a second electronic component chip. The base includes a first surface and a second surface. The first plated layer covers the first surface. The first electronic component chip is provided on the first plated layer with a first insulating layer being interposed therebetween. The second plated layer covers the second surface. The second electronic component chip is provided on the second plated layer with a second insulating layer being interposed therebetween. The first plated layer and the second plated layer each include a first metal material that is less likely to undergo an ion migration phenomenon than silver (Ag).

An electronic component package of an embodiment of the disclosure includes a base, a first plated layer, a first electronic component chip, a second plated layer, and a second electronic component chip. The base includes a first surface and a second surface. The first plated layer covers the first surface. The first electronic component chip is provided on the first plated layer with a first insulating layer being interposed therebetween. The second plated layer covers the second surface. The second electronic component chip is provided on the second plated layer with a second insulating layer being interposed therebetween. The first plated layer and the second plated layer each include a first metal material that is less likely to undergo an ion migration phenomenon than silver (Ag).

A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.

A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.

A photocoupler of an embodiment includes an input terminal, an output terminal, a first MOSFET, a second MOSFET, a semiconductor light receiving element, a semiconductor light emitting element, and a resin layer. The first MOSFET is joined onto the third lead. The second MOSFET is joined onto the fourth lead. The semiconductor light receiving element is joined to each of the first junction region and the second junction region. The semiconductor light receiving element includes a light receiving region provided in a central part of a surface on opposite side from a surface joined to the first and second MOSFET. The resin layer seals the first and second MOSFETs, the semiconductor light receiving element, the semiconductor light emitting element, an upper surface and a side surface of the input terminal, and an upper surface and a side surface of the output terminal.

A photocoupler of an embodiment includes an input terminal, an output terminal, a first MOSFET, a second MOSFET, a semiconductor light receiving element, a semiconductor light emitting element, and a resin layer. The first MOSFET is joined onto the third lead. The second MOSFET is joined onto the fourth lead. The semiconductor light receiving element is joined to each of the first junction region and the second junction region. The semiconductor light receiving element includes a light receiving region provided in a central part of a surface on opposite side from a surface joined to the first and second MOSFET. The resin layer seals the first and second MOSFETs, the semiconductor light receiving element, the semiconductor light emitting element, an upper surface and a side surface of the input terminal, and an upper surface and a side surface of the output terminal.

A die bonding apparatus includes: a mounting base including a mounting area on which a first member is mounted; a heater arranged below the mounting base; a side wall configured to surround the mounting area; a collet configured to hold a second member by vacuum-chucking at an end portion; a lid including a hole, the lid being mounted on the side wall; a moving structure configured to move the collet to transport the second member held by the collet through the hole for bonding the second member to the first member; and a gas-supplying tube arranged on the side wall and configured to supply a heating gas to a heating space formed by the side wall and the lid. The lid contains a material capable of: reflecting an infrared radiation caused by the heater and the heating gas; or absorbing and re-radiating the infrared radiation.