The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.

A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.

A semiconductor device includes: a first semiconductor chip having a first electrode and a second electrode on a first surface and having a third electrode on a second surface that is opposite to the first surface; a second semiconductor chip having a first electrode and a second electrode on a first surface and having a third electrode on a second surface that is opposite to the first surface; a first electrode plate bonded to the second electrode of the first semiconductor chip by a bonding material; a second electrode plate bonded to the third electrode of the second semiconductor chip by a bonding material; and a third electrode plate placed between the first semiconductor chip and the second semiconductor chip and having a first area sandwiched between the first semiconductor chip and the second semiconductor chip and a second area not sandwiched between the first semiconductor chip and the second semiconductor chip, wherein one surface of the first area of the third electrode plate is bonded to the second electrode of the second semiconductor chip by a bonding material, and another surface of the first area of the third electrode plate is bonded to the third electrode of the first semiconductor chip by a bonding material, and wherein in the third electrode plate, the first area is thinner than the second area.

A semiconductor device includes: a first semiconductor chip having a first electrode and a second electrode on a first surface and having a third electrode on a second surface that is opposite to the first surface; a second semiconductor chip having a first electrode and a second electrode on a first surface and having a third electrode on a second surface that is opposite to the first surface; a first electrode plate bonded to the second electrode of the first semiconductor chip by a bonding material; a second electrode plate bonded to the third electrode of the second semiconductor chip by a bonding material; and a third electrode plate placed between the first semiconductor chip and the second semiconductor chip and having a first area sandwiched between the first semiconductor chip and the second semiconductor chip and a second area not sandwiched between the first semiconductor chip and the second semiconductor chip, wherein one surface of the first area of the third electrode plate is bonded to the second electrode of the second semiconductor chip by a bonding material, and another surface of the first area of the third electrode plate is bonded to the third electrode of the first semiconductor chip by a bonding material, and wherein in the third electrode plate, the first area is thinner than the second area.

Various apparatus and methods are disclosed. In one aspect, a method of manufacturing a thermal interface material on a semiconductor chip is provided. The method includes placing a preform of a combination of a first metal and a second metal on one of the semiconductor chip or a lid. The preform is liquid phase sintered to cause the combination to evolve to an equilibrium composition and bond to the semiconductor chip.

Various apparatus and methods are disclosed. In one aspect, a method of manufacturing a thermal interface material on a semiconductor chip is provided. The method includes placing a preform of a combination of a first metal and a second metal on one of the semiconductor chip or a lid. The preform is liquid phase sintered to cause the combination to evolve to an equilibrium composition and bond to the semiconductor chip.