According to one embodiment, a semiconductor device includes a semiconductor chip having a first electrode on a first surface, a metal plate, and a first conductive bonding sheet that is disposed between the first surface of the semiconductor chip and the metal plate and bonds the first electrode to the metal plate.

According to one embodiment, a semiconductor device includes a semiconductor chip having a first electrode on a first surface, a metal plate, and a first conductive bonding sheet that is disposed between the first surface of the semiconductor chip and the metal plate and bonds the first electrode to the metal plate.

A semiconductor device according to an embodiment includes a base frame, a semiconductor element provided on the base frame, a connector provided on the semiconductor element, the connector having an upper surface, a side surface, and a porous body having a plurality of pores provided on at least the side surface, and a molded resin provided in a periphery of the semiconductor element and at least the side surface of the connector. The upper surface of the connector is exposed.

A semiconductor device according to an embodiment includes a base frame, a semiconductor element provided on the base frame, a connector provided on the semiconductor element, the connector having an upper surface, a side surface, and a porous body having a plurality of pores provided on at least the side surface, and a molded resin provided in a periphery of the semiconductor element and at least the side surface of the connector. The upper surface of the connector is exposed.

Provided is a semiconductor device including: a bed having a bed surface; a semiconductor chip having a bottom surface larger than the bed surface, the semiconductor chip being provided such that a center of the bottom surface is disposed above the bed surface and the bottom surface having a first end and a second end; a joint material provided between the bed surface and the bottom surface; a plate-like first wire having a first surface and provided such that the first surface faces the first end; a plate-like second wire having a second surface and provided such that the second surface faces the second end; a first insulating film having a third surface and a fourth surface provided on an opposite side of the third surface, the third surface being in contact with the first end, the fourth surface being in contact with the first surface; and a second insulating film having a fifth surface and a sixth surface provided on an opposite side of the fifth surface, the fifth surface being in contact with the second end, the sixth surface being in contact with the first surface.

Provided is a semiconductor device including: a bed having a bed surface; a semiconductor chip having a bottom surface larger than the bed surface, the semiconductor chip being provided such that a center of the bottom surface is disposed above the bed surface and the bottom surface having a first end and a second end; a joint material provided between the bed surface and the bottom surface; a plate-like first wire having a first surface and provided such that the first surface faces the first end; a plate-like second wire having a second surface and provided such that the second surface faces the second end; a first insulating film having a third surface and a fourth surface provided on an opposite side of the third surface, the third surface being in contact with the first end, the fourth surface being in contact with the first surface; and a second insulating film having a fifth surface and a sixth surface provided on an opposite side of the fifth surface, the fifth surface being in contact with the second end, the sixth surface being in contact with the first surface.

A semiconductor package assembly includes a carrier with a die attach surface and a contact pad separated from the die attach surface, a semiconductor die mounted on the die attach surface, the semiconductor die having a front side metallization that faces away from the die attach surface, an interconnect ribbon attached to the semiconductor die and the contact pad such that the interconnect ribbon electrically connects the front side metallization to the contact pad, and an electrically insulating encapsulant body that encapsulates the semiconductor die and at least part of the interconnect ribbon. The interconnect ribbon includes a layer stack of a first metal layer and a second layer formed on top of the first metal layer. The first metal layer includes a different metal as the second metal layer. The first metal layer faces the front side metallization.

A semiconductor package assembly includes a carrier with a die attach surface and a contact pad separated from the die attach surface, a semiconductor die mounted on the die attach surface, the semiconductor die having a front side metallization that faces away from the die attach surface, an interconnect ribbon attached to the semiconductor die and the contact pad such that the interconnect ribbon electrically connects the front side metallization to the contact pad, and an electrically insulating encapsulant body that encapsulates the semiconductor die and at least part of the interconnect ribbon. The interconnect ribbon includes a layer stack of a first metal layer and a second layer formed on top of the first metal layer. The first metal layer includes a different metal as the second metal layer. The first metal layer faces the front side metallization.

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.