The present application provides a method for fabricating a semiconductor device. The method includes providing a carrier substrate, forming through semiconductor vias in the carrier substrate for thermally conducting heat, forming a bonding layer on the carrier substrate, providing a first die structure including through semiconductor vias, forming an intervening bonding layer on the first die structure, bonding the first die structure onto the bonding layer through the intervening bonding layer, and bonding a second die structure onto the first die structure. The carrier substrate, the through semiconductor vias, and the bonding layer together configure a carrier structure. The second die structure and the first die structure are electrically coupled by the through semiconductor vias.

Embodiments of the disclosure relate to flexible electronic substrates for placement on an external surface of a vehicle motor assembly. In one embodiment, a motor assembly includes a motor comprising an external surface and one or more electronic assemblies positioned on the external surface of the motor. Each electronic assembly includes a metal substrate disposed on the external surface of the motor, a dielectric layer disposed on the metal substrate, a flexible metal base layer disposed on the dielectric layer, a bonding layer disposed on the flexible metal base layer, and one or more electronic devices disposed on the bonding layer. The bonding layer bonds the one or more electronic devices to the flexible metal base layer.

Embodiments of the disclosure relate to flexible electronic substrates for placement on an external surface of a vehicle motor assembly. In one embodiment, a motor assembly includes a motor comprising an external surface and one or more electronic assemblies positioned on the external surface of the motor. Each electronic assembly includes a metal substrate disposed on the external surface of the motor, a dielectric layer disposed on the metal substrate, a flexible metal base layer disposed on the dielectric layer, a bonding layer disposed on the flexible metal base layer, and one or more electronic devices disposed on the bonding layer. The bonding layer bonds the one or more electronic devices to the flexible metal base layer.

Embodiments of the disclosure relate to flexible electronic substrates for placement on an external surface of a vehicle motor assembly. In one embodiment, a motor assembly includes a motor comprising an external surface and one or more electronic assemblies positioned on the external surface of the motor. Each electronic assembly includes a metal substrate disposed on the external surface of the motor, a dielectric layer disposed on the metal substrate, a flexible metal base layer disposed on the dielectric layer, a bonding layer disposed on the flexible metal base layer, and one or more electronic devices disposed on the bonding layer. The bonding layer bonds the one or more electronic devices to the flexible metal base layer.

Embodiments of the disclosure relate to flexible electronic substrates for placement on an external surface of a vehicle motor assembly. In one embodiment, a motor assembly includes a motor comprising an external surface and one or more electronic assemblies positioned on the external surface of the motor. Each electronic assembly includes a metal substrate disposed on the external surface of the motor, a dielectric layer disposed on the metal substrate, a flexible metal base layer disposed on the dielectric layer, a bonding layer disposed on the flexible metal base layer, and one or more electronic devices disposed on the bonding layer. The bonding layer bonds the one or more electronic devices to the flexible metal base layer.

One aspect of the invention is a method of manufacturing a connection structure, including disposing an adhesive layer between a first electronic member including a first substrate and a first electrode formed on the first substrate and a second electronic member including a second substrate and a second electrode formed on the second substrate, and pressure-bonding the first electronic member and the second electronic member via the adhesive layer such that the first electrode and the second electrode are electrically connected to each other, wherein the first electronic member further including an insulating layer formed on a side of the first electrode opposite to the first substrate, and the adhesive layer including: a first conductive particle being a dendritic conductive particle; and a second conductive particle being a conductive particle other than the first conductive particle and having a non-conductive core and a conductive layer provided on the core.

One aspect of the invention is a method of manufacturing a connection structure, including disposing an adhesive layer between a first electronic member including a first substrate and a first electrode formed on the first substrate and a second electronic member including a second substrate and a second electrode formed on the second substrate, and pressure-bonding the first electronic member and the second electronic member via the adhesive layer such that the first electrode and the second electrode are electrically connected to each other, wherein the first electronic member further including an insulating layer formed on a side of the first electrode opposite to the first substrate, and the adhesive layer including: a first conductive particle being a dendritic conductive particle; and a second conductive particle being a conductive particle other than the first conductive particle and having a non-conductive core and a conductive layer provided on the core.

A micro-bonding structure including a substrate, a conductive pad, a bonding layer, a micro device, and a diffusive bonding portion is provided. The conductive pad is present on the substrate. The bonding layer is present on the conductive pad. The micro device is present on the bonding layer. The diffusive bonding portion is present between and electrically connected with the bonding layer and the conductive pad. The diffusive bonding portion consists of at least a part of elements from the bonding layer and at least a part of elements from the conductive pad. A plurality of voids are present between the bonding layer and the conductive pad, and one of the voids is bounded by the diffusive bonding portion and at least one of the conductive pad and the bonding layer.

A micro-bonding structure including a substrate, a conductive pad, a bonding layer, a micro device, and a diffusive bonding portion is provided. The conductive pad is present on the substrate. The bonding layer is present on the conductive pad. The micro device is present on the bonding layer. The diffusive bonding portion is present between and electrically connected with the bonding layer and the conductive pad. The diffusive bonding portion consists of at least a part of elements from the bonding layer and at least a part of elements from the conductive pad. A plurality of voids are present between the bonding layer and the conductive pad, and one of the voids is bounded by the diffusive bonding portion and at least one of the conductive pad and the bonding layer.

A semiconductor chip includes a semiconductor body having a lower side with a lower chip metallization applied thereto. A first contact metallization layer is produced on the lower chip metallization. A second contact metallization layer is produced on a metal surface of a substrate. The semiconductor chip and the substrate are pressed onto one another for a pressing time so that the first and second contact metallization layers bear directly and extensively on one another. During the pressing time, the first contact metallization layer is kept continuously at temperatures which are lower than the melting temperature of the first contact metallization layer. The second contact metallization layer is kept continuously at temperatures which are lower than the melting temperature of the second contact metallization layer during the pressing time. After the pressing together, the first and second contact metallization layers have a total thickness less than 1000 nm.