A circuit package for electrically connecting a plurality of modules. The circuit package having a first and second mounting plate, each including a plurality of module connectors configured to receive and form electrical connections with the plurality of modules. The circuit package also having a first and second sidewall mounted to the first and second mounting plates. The first sidewall including a plurality of sidewall fins extending outward from the first sidewall so that the plurality of sidewall fins are positioned between the first and second mounting plates and at least partially interleave with the plurality of modules.

A circuit package for electrically connecting a plurality of modules. The circuit package having a first and second mounting plate, each including a plurality of module connectors configured to receive and form electrical connections with the plurality of modules. The circuit package also having a first and second sidewall mounted to the first and second mounting plates. The first sidewall including a plurality of sidewall fins extending outward from the first sidewall so that the plurality of sidewall fins are positioned between the first and second mounting plates and at least partially interleave with the plurality of modules.

A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

A vibrator device has a base that has a first terminal, a circuit element that is disposed on the base and has a second terminal, a vibrator that includes a vibrator element and a vibrator element package, and is positioned between the first terminal and the second terminal in plan view of the base, a wiring unit that is disposed on the vibrator, a first wire that electrically connects the first terminal and the wiring unit together, and a second wire that electrically connects the wiring unit and the second terminal together.

A vibrator device has a base that has a first terminal, a circuit element that is disposed on the base and has a second terminal, a vibrator that includes a vibrator element and a vibrator element package, and is positioned between the first terminal and the second terminal in plan view of the base, a wiring unit that is disposed on the vibrator, a first wire that electrically connects the first terminal and the wiring unit together, and a second wire that electrically connects the wiring unit and the second terminal together.

Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like. A hollow portion 9 in which the semiconductor circuit 3 is housed in an airtight state is provided between the device substrate 2 and the cap substrate 8. The bump portion 14 connects all the via portions 10 and the cap substrate 8. Thus, the via portions 10 can be reinforced using the bump portion 14A.

Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like. A hollow portion 9 in which the semiconductor circuit 3 is housed in an airtight state is provided between the device substrate 2 and the cap substrate 8. The bump portion 14 connects all the via portions 10 and the cap substrate 8. Thus, the via portions 10 can be reinforced using the bump portion 14A.

According to one embodiment, a semiconductor device includes a chip having a first surface and a second surface, a first electrode pad provided on the first surface of the chip, a first conductive layer provided above the first electrode pad, a first bonding material that is provided between the first electrode pad and the first conductive layer and is in contact with the first electrode pad and the first conductive layer, and a second electrode pad provided on the second surface of the chip. A third surface of the first bonding material facing the first electrode pad has a contact portion in contact with the first electrode pad and a notch portion surrounding the contact portion. An end of the contact portion is located inside an end surface of the first conductive layer.