A manufacturing method of a package-on package structure including at least the following steps is provided. A die is bonded on a first circuit carrier. A spacer is disposed on the die. The spacer and the first circuit carrier are connected through a plurality of conductive wires. An encapsulant is formed to encapsulate the die, the spacer and the conductive wires. A thickness of the encapsulant is reduced until at least a portion of each of the conductive wires is removed to form a first package structure. A second package structure is stacked on the first package structure. The second package structure is electrically connected to the conductive wires.

A manufacturing method of a package-on package structure including at least the following steps is provided. A die is bonded on a first circuit carrier. A spacer is disposed on the die. The spacer and the first circuit carrier are connected through a plurality of conductive wires. An encapsulant is formed to encapsulate the die, the spacer and the conductive wires. A thickness of the encapsulant is reduced until at least a portion of each of the conductive wires is removed to form a first package structure. A second package structure is stacked on the first package structure. The second package structure is electrically connected to the conductive wires.

A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the substrate via the first conductive connectors.

A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the substrate via the first conductive connectors.

A method of forming a package-on-package (POP) structure is provided. A laser drilling is performed on a mold compound of a first semiconductor package to form a plurality of through holes in the mold compound. A conductive layer is formed on the mold compound such that the mold compound is covered by a conductive material and the through holes are filled with the conductive material. The layer of the conductive material is grinded to expose the mold compound. A second semiconductor package is stacked on the first semiconductor package such that a plurality of metal bumps of the second semiconductor package attach to the conductive material filled in the through holes.

A method of forming a package-on-package (POP) structure is provided. A laser drilling is performed on a mold compound of a first semiconductor package to form a plurality of through holes in the mold compound. A conductive layer is formed on the mold compound such that the mold compound is covered by a conductive material and the through holes are filled with the conductive material. The layer of the conductive material is grinded to expose the mold compound. A second semiconductor package is stacked on the first semiconductor package such that a plurality of metal bumps of the second semiconductor package attach to the conductive material filled in the through holes.

Apparatus and method for tool mark free stich bonding. In some embodiments, a method for wire bonding can include feeding a wire through a capillary tip and attaching a first end of the wire to a first location, thereby forming a ball bond. The method can further include moving the capillary tip towards a second location while the wire feeds out of the capillary tip. The method can further include attaching a second end of the wire to the second location while preventing contact between the capillary tip and the second location, thereby forming a stitch bond without a tool mark at the second location.

A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k+1th semiconductor chip when k is 1.

The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction.

Leadless electronic packages for GaN-based half bridge power conversion circuits have low inductance internal and external connections, high thermal conductivity and a large separation between external connections for use in high voltage power conversion circuits. Some electronic packages employ L shaped power paths and internal low impedance die to die connections. Further embodiments employ an insulative substrate disposed within the electronic package for efficient power path routing and increased packaging density.