Method of forming package-on-package structure

Abstract

A method of forming a package-on-package (POP) structure is provided. A laser drilling is performed on a mold compound of a first semiconductor package to form a plurality of through holes in the mold compound. A conductive layer is formed on the mold compound such that the mold compound is covered by a conductive material and the through holes are filled with the conductive material. The layer of the conductive material is grinded to expose the mold compound. A second semiconductor package is stacked on the first semiconductor package such that a plurality of metal bumps of the second semiconductor package attach to the conductive material filled in the through holes.

Claims

1. A method of forming a package-on-package (POP) structure, the method comprising: performing a laser drilling on a mold compound of a first semiconductor package to form a plurality of through holes in the mold compound; forming a conductive layer on the mold compound such that the mold compound is covered by a conductive material and the through holes are filled with the conductive material; grinding the conductive layer to expose the mold compound; and stacking a second semiconductor package on the first semiconductor package such that a plurality of metal bumps of the second semiconductor package attach to the conductive material filled in the through holes.

2. The method of claim 1, wherein forming the conductive layer on the mold compound includes sputtering the conductive material on the mold compound.

3. The method of claim 1, wherein forming the conductive layer on the mold compound includes electroplating the conductive material on the mold compound.

4. The method of claim 1, wherein the conductive material is copper.

5. The method of claim 1, wherein the conductive material is gold.

6. The method of claim 1, wherein the conductive material is a copper gold alloy.

7. The method of claim 1, wherein the first semiconductor package is a flip-chip package.

8. The method of claim 1, wherein the first semiconductor package comprises a first die and a first substrate, a circuitry is formed in the first substrate, and the first die is electrically connected to the circuitry via a plurality of bonding wires.

9. The method of claim 1, wherein the first semiconductor package comprises a first die, a first substrate and a plurality of conductive pads, the first die is disposed on the first substrate and encapsulated by the mold compound, and the conductive pads are exposed on bottoms of the through holes after performing the laser drilling.

10. The method of claim 9, wherein the first semiconductor package further comprises a plurality of conductive pillars formed in the first substrate and a plurality of metal bumps formed below the first substrate, and the conductive pads are electrically connected to some of the metal bumps of the first semiconductor package via the conductive pillars.

11. The method of claim 1, wherein the second semiconductor package comprises a second die, the first semiconductor package comprises a first die, a first substrate, a plurality of conductive pillars and a plurality of metal bumps, the first die is disposed on the first substrate and encapsulated by the mold compound, the conductive pillars are formed in the first substrate, the metal bumps of the first semiconductor package are formed below the first substrate, the conductive material filled in the through holes forms a plurality of through hole vias, and the second die is electrically connected to some of the metal bumps of the first semiconductor package via the metal bumps of the second semiconductor package, the through hole vias and the conductive pillars.

12. The method of claim 11, wherein the second semiconductor package further comprises a plurality of pillar bumps electrically connected to the metal bumps of the second semiconductor package.

13. The method of claim 11, wherein the second semiconductor package further comprises a second substrate, the second die is disposed on the second substrate, and the metal bumps of the second semiconductor package are formed below the second substrate.

14. The method of claim 1, wherein the conductive material filled in the through holes forms a plurality of through hole vias, and a height of each through hole via is between 200 micrometers to 300 micrometers.

15. The method of claim 1, wherein the conductive material filled in the through holes forms a plurality of through hole vias, and a distance between bottoms of two adjacent through hole vias is less than 300 micrometers.

16. The method of claim 1, wherein the mold compound is epoxy molding compound.

17. The method of claim 1, wherein the second semiconductor package is a flip-chip package.

18. The method of claim 1, wherein the first semiconductor package is a fan-out package.

19. The method of claim 1, wherein the second semiconductor package is a fan-out package.

20. The method of claim 1, wherein the conductive material filled in the through holes forms a plurality of through hole vias, and the metal bumps of the second semiconductor package are bonded to the through hole vias by performing a reflow soldering process.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIGS. 1 to 6 are component cross-sectional views showing corresponding processing steps of the method of forming a package-on-package (POP) structure according to a first embodiment of the present invention.

[0007] FIGS. 7 to 12 are component cross-sectional views showing corresponding processing steps of the method of forming a POP structure according to a second embodiment of the present invention.

DETAILED DESCRIPTION

[0008] With reference to the attached drawings, the present invention is described by means of the embodiment(s) below where the attached drawings are simplified for illustration purposes only to illustrate the structures or methods of the present invention by describing the relationships between the components and assembly in the present invention. Therefore, the components shown in the figures are not expressed with the actual numbers, actual shapes, actual dimensions, nor with the actual ratio. Some of the dimensions or dimension ratios have been enlarged or simplified to provide a better illustration. The actual numbers, actual shapes, or actual dimension ratios can be selectively designed and disposed and the detail component layouts may be more complicated.

[0009] According to a first embodiment of the present invention, a method of forming a package-on-package (POP) structure is illustrated in FIGS. 1 to 6 for a cross-sectional view.

[0010] As shown in FIG. 1, a first semiconductor package 100 is provided. The first semiconductor package 100 comprises a first die 110, a mold compound 120, a plurality of conductive pads 132, a substrate 140 and a plurality of metal bumps 150. The first die 110 and the conductive pads 132 are disposed on the substrate 140 and encapsulated by the mold compound 120. The metal bumps 150 are formed below the substrate 140. In the embodiment, the first semiconductor package 100 is a flip-chip package, but the present invention is not limited thereto. The first die 110 has a plurality of pillar bumps 112 disposed on the substrate 140 and electrically connected to some of the metal bumps 150. The pillar bumps 112 are used as an I/O interface of the first die 110. The substrate 140 may comprise a pad mask layer 130 and a plurality of conductive pillars 142. The conductive pillars 142 are formed in the substrate 140 and pass through the substrate 140. Some of the metal bumps 150 are electrically connected to the conductive pads 132 via the conductive pillars 142. In the embodiment, the first semiconductor package 100 may be a fan-out package.

[0011] As shown in FIG. 2, a laser drilling is performed on the mold compound 120 to form a plurality of through holes 122 in the mold compound 120, such that the conductive pads 132 are exposed on bottoms of the through holes 122.

[0012] As shown in FIG. 3, a conductive layer 160 is formed on the mold compound 120 such that the mold compound 120 is covered by a conductive material and the through holes 122 are filled with the conductive material. The conductive material may be copper (Cu), gold (Au) or a copper gold (Au-Cu) alloy. The conductive layer 160 may be formed on the mold compound 120 by sputtering or electroplating the conductive material on the mold compound 120.

[0013] As shown in FIG. 4, the conductive layer 160 is grinded to expose the mold compound 120. Accordingly, the conductive material filled in the through holes 122 forms a plurality of through hole vias 160A. The through hole vias 160A are in contact with the conductive pads 132. A height H of each through hole via 160A may range from 200 micrometers to 300 micrometers. A distance D between bottoms of two adjacent through hole vias 160A may be less than 300 micrometers. In another embodiment, the mold compound 120 may be grinded when grinding the conductive layer 160. Since the conductive layer 160 and the mold compound 120 may be grinded, the thickness of the first semiconductor package 100 may be reduced. In another embodiment, the substrate 140 of the first semiconductor package 100 may be removed after the through hole vias 160A are formed. Accordingly, the thickness of the first semiconductor package 100 may be further reduced.

[0014] As shown in FIGS. 5 and 6, a second semiconductor package 200 is stacked on the first semiconductor package 100. A plurality of metal bumps 250 of the second semiconductor package 200 are attached to the through hole vias 160A when the second semiconductor package 200 is stacked on the first semiconductor package 100. The metal bumps 250 of the second semiconductor package 200 may be attached to the exposed surface of through hole vias 160A by performing a reflow soldering process. As a result, the first semiconductor package 100 and the second semiconductor package 200 are integrated as a package-on-package (POP) structure 300. Since the through holes 122 are formed by performing a laser drilling, the POP structure 300 would be a fine pitch package.

[0015] In the embodiment, the second semiconductor package 200 may be a fan-out package and/or a flip-chip package, but the present invention is not limited thereto. The second semiconductor package 200 comprises a second die 210, a mold compound 220, a substrate 240 and the metal bumps 250. The second die 210 is disposed on the substrate 240 and encapsulated by the mold compound 220. The metal bumps 250 are formed below the substrate 240. The second die 210 is electrically connected to some of the metal bumps 150 of the first semiconductor package 100 via the metal bumps 250 of the second semiconductor package 200, the through hole vias 160A and the conductive circuit of the substrate 140. The second die 210 comprises a plurality of pillar bumps 212. The conductive pillars 242 are disposed in the substrate 240 and electrically connected to the metal bumps 250.

[0016] According to a second embodiment of the present invention, another method of forming a POP structure is illustrated in FIGS. 7 to 12 for a cross-sectional view. The same reference numbers used in the first embodiment and the second embodiment represent the same elements.

[0017] As shown in FIG. 7, a first semiconductor package 400 according to another embodiment is provided. The major difference between the two semiconductor packages 100 and 400 is that the first die 110 in FIG. 7 is coupled to the substrate 140 through wire bonding. The first die 110 is coupled to a circuitry formed in the substrate 140 via a plurality of wires 114. The circuitry formed in the substrate 140 is electrically connected to some of the metal bumps 150.

[0018] As shown in FIG. 8, a laser drilling is performed on the mold compound 120 to form a plurality of through holes 122 in the mold compound 120, such that the conductive pads 132 are exposed on bottoms of the through holes 122.

[0019] As shown in FIG. 9, a conductive layer 160 is form on the mold compound 120 such that the through holes 122 are filled with the conductive material and the mold compound 120 is covered by the conductive material.

[0020] As shown in FIG. 10, the conductive layer 160 is grinded to expose the mold compound 120. Accordingly, the conductive material filled in the through holes 122 forms a plurality of through hole vias 160A. The through hole vias 160A may be in contact with the conductive pads 132. A height H of each through hole via 160A may be range from 200 micrometers to 300 micrometers. A distance D between bottoms of two adjacent through hole vias 160A may be less than 300 micrometers. In another embodiment, the mold compound 120 may be grinded when grinding the conductive layer 160. Since the conductive layer 160 and the mold compound 120 may be grinded, the thickness of the first semiconductor package 400 may be reduced.

[0021] As shown in FIGS. 11 and 12, the second semiconductor package 200 is stacked on the first semiconductor package 400. A plurality of metal bumps 250 of the second semiconductor package 200 are attached to the through hole vias 160A when the second semiconductor package 200 is stacked on the first semiconductor package 400. The metal bumps 250 of the second semiconductor package 200 may be bonded to the through hole vias 160A of the first semiconductor package 400 by performing a reflow soldering process. As a result, the first semiconductor package 400 and the second semiconductor package 200 are integrated as a package-on-package (POP) structure 500.

[0022] In summary, a laser drilling is performed to form a plurality of through holes in the mold compound, and the through holes are filled with the conductive material to form a plurality of through hole vias. The distance between the bottoms of two adjacent through hole vias may be less than 300 micrometers. Thereby, the POP structure would be a fine pitch package. Moreover, the conductive layer and the mold compound may be grinded, and the substrate of the first semiconductor package may be removed after the through hole vias are formed. Accordingly, the thickness of the POP structure would be reduced.

[0023] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.