A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k−1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k+1th semiconductor chip when k is 1.

A light-emitting device includes a plurality of plate-shaped base materials, an insulating coating film, and at least one light-emitting element. The base materials are arranged side by side to be mutually spaced. The insulating coating film is formed to cover an upper surface and a side surface of each of the plurality of base materials. The coating film is provided with an opening portion that exposes one region of the upper surface of one base material and includes a binding portion mutually binding the plurality of base materials. The at least one light-emitting element is placed on the one region. The coating film includes a thin film portion in which the coating film is formed in a thin film to surround an outer peripheral end of the opening portion.

A method and a device for establishing a wire connection between a first contact surface and at least one further contact surface. A contact end of a wire is positioned in a contact position relative to the first contact surface with a wire guiding tool. Subsequently, a mechanical, electrically conductive connection is established between the first contact surface and the contact end with a first solder material connection, and subsequently the wire guiding tool is moved to the further contact surface thus forming a wire section and establishing a further mechanical, electrically conductive connection between the wire section end and the further contact surface with a further solder material connection.

It is an object to enable a non-destructive inspection of reliability of a bonding part and enabling an accurate inspection. A wedge tool includes: a groove which is formed along a direction of an ultrasonic vibration in a tip portion and in which a bonding wire is disposed in a wedge bonding; a first planar surface and a second planar surface disposed on both sides of the groove; and at least one convex portion formed away from the groove in at least one of the first planar surface and the second planar surface, wherein the bonding wire comes in contact with the convex portion by a deformation of the bonding wire in a bonding part of the bonding wire and a bonded object bonded to each other by a wedge bonding.

A semiconductor structure is disclosed. The semiconductor structure includes a substrate an elastomer coupled to the substrate and a plurality of bondfingers on the elastomer. The substrate, the elastomer and the bondfingers are configured to cooperatively expand and retract.

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

To arrange a protective material horizontally with respect to a substrate plane without the protective material coming into contact with wires in a wire-bonded semiconductor package.

The semiconductor package includes a protective material, a substrate, bumps, and a semiconductor chip. The bumps are provided on a chip plane of the semiconductor chip and are connected to the substrate via wires. The semiconductor chip is laminated on the substrate. A support is provided on the chip plane to support the protective material at a position where the height from the chip plane of the semiconductor chip is higher than the bumps.

A chip package structure and an electronic equipment may reduce probability of short circuit failure during chip packaging and improve chip reliability. The chip package structure includes: a chip, a substrate, and a lead; the chip is disposed above the substrate; wherein the chip includes a pin pad and a test metal key, and the lead is configured to electrically connect the pin pad and the substrate; the test metal key is disposed in an edge region of the chip that is not under the lead.

An image sensor package includes a circuit board, an image sensor chip on the circuit board, a stack bump structure on the image sensor chip, a bonding wire connecting the circuit board to the stack bump structure, a dam element on the image sensor chip and covering both the stack bump structure and the bonding wire, and a molding element contacting the dam element on the circuit board and covering both the image sensor chip and the bonding wire.