A semiconductor package including a redistribution substrate with a first insulating layer, one or more second insulating layers on the first insulating layer, and a plurality of redistribution layers. The first insulating layer includes a first photosensitive resin having an elongation of 60% or more and toughness of 70 mJ/mm.sup.3 or more. The one or more second insulating layers include a second photosensitive resin having an elongation in a range of 10% to 40% and toughness of 40 mJ/mm.sup.3.

A semiconductor package including a redistribution substrate with a first insulating layer, one or more second insulating layers on the first insulating layer, and a plurality of redistribution layers. The first insulating layer includes a first photosensitive resin having an elongation of 60% or more and toughness of 70 mJ/mm.sup.3 or more. The one or more second insulating layers include a second photosensitive resin having an elongation in a range of 10% to 40% and toughness of 40 mJ/mm.sup.3.

Each of a plurality of semiconductor elements included in a semiconductor package includes a front-surface electrode being provided on a semiconductor substrate on a side opposite to a conductor substrate, a back-surface electrode being joined to the conductor substrate, a control pad configured to control current flowing between the front-surface electrode and the back-surface electrode, a frame being electrically connected to the front-surface electrode, a portion of the frame being exposed from a surface of a sealing material from which a lower surface of the conductor substrate is exposed, and a plurality of terminal blocks being electrically connected to a plurality of first pads, a portion of the plurality of terminal blocks being exposed from a surface of the sealing material, the surface being provided on a side opposite to the surface of the sealing material from which the lower surface of the conductor substrate is exposed.

Each of a plurality of semiconductor elements included in a semiconductor package includes a front-surface electrode being provided on a semiconductor substrate on a side opposite to a conductor substrate, a back-surface electrode being joined to the conductor substrate, a control pad configured to control current flowing between the front-surface electrode and the back-surface electrode, a frame being electrically connected to the front-surface electrode, a portion of the frame being exposed from a surface of a sealing material from which a lower surface of the conductor substrate is exposed, and a plurality of terminal blocks being electrically connected to a plurality of first pads, a portion of the plurality of terminal blocks being exposed from a surface of the sealing material, the surface being provided on a side opposite to the surface of the sealing material from which the lower surface of the conductor substrate is exposed.

A description is given of a power semiconductor module 10 which can be transferred from a normal operating mode to an explosion-free robust short-circuit failure mode. Said power semiconductor module 10 comprises a power semiconductor 1 having metallizations 3 which form potential areas and are separated by insulations and passivations on the top side 2 of said power semiconductor. Furthermore, an electrically conductive connecting layer is provided, on which at least one metal shaped body 4 which has a low lateral electrical resistance and is significantly thicker than the connecting layer is arranged, said at least one metal shaped body being applied by sintering of the connecting layer such that said metal shaped body is cohesively connected to the respective potential area. The metal shaped body 4 is embodied and designed with means for laterally homogenizing a current flowing through it in such a way that a lateral current flow component 5 is maintained until this module switches off in order to avoid an explosion, wherein the metal shaped body 4 has connections 6 having high-current capability. A transition from the operating mode to the robust failure mode then takes place in an explosion-free manner by virtue of the fact that the connections 6 are contact-connected and dimensioned in such a way that in the case of overload currents of greater than a multiple of the rated current of the power semiconductor 1, the operating mode changes to the short-circuit failure mode with connections 6 remaining on the metal shaped body 4 in an explosion-free manner without the formation of arcs.

A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.

A die package having lead structures connecting to a die that provide for electromagnetic interference reductions. Mixed impedance leads connected to the die have a first lead with a first metal core, a dielectric layer surrounding the first metal core, and first outer metal layer connected to ground; and a second lead with a second metal core, and a second dielectric layer surrounding the second metal core, and a second outer metal layer connected to ground. Each lead reducing susceptibility to EMI and crosstalk.

A semiconductor device includes a lead frame having a first principal surface which includes a recess, and a second principal surface opposite to the first principal surface, a relay board, disposed in the recess, and having a third principal surface, and a fourth principal surface opposite to the third principal surface, wherein the fourth principal surface opposes a bottom surface of the recess, a first semiconductor chip disposed on the third principal surface, a first conductive material connecting the lead frame and the relay board, and a second conductive material connecting the relay board and the first semiconductor chip. A distance between the second principal surface and the third principal surface is less than or equal to a distance between the second principal surface and the first principal surface.

A semiconductor device includes a semiconductor substrate with a wiring layer formed thereon, an insulating film formed on the semiconductor substrate so as to cover the wiring layer and having a pad opening exposing a portion of the wiring layer as a pad, a front surface protection film formed on the insulating film and being constituted of an insulating material differing from the insulating film and having a second pad opening securing exposure of at least a portion of the pad, a seed layer formed on the pad, and a plating layer formed on the seed layer.

A semiconductor device includes a semiconductor substrate with a wiring layer formed thereon, an insulating film formed on the semiconductor substrate so as to cover the wiring layer and having a pad opening exposing a portion of the wiring layer as a pad, a front surface protection film formed on the insulating film and being constituted of an insulating material differing from the insulating film and having a second pad opening securing exposure of at least a portion of the pad, a seed layer formed on the pad, and a plating layer formed on the seed layer.