The sinter-bonding composition contains sinterable particles containing an electroconductive metal. The average particle diameter of the sinterable particles is 2 μm or less and the proportion of the particles having a particle diameter of 100 nm or less in the sinterable particles is not less than 40% by mass and less than 80% by mass. The sinter-bonding sheet (10) has an adhesive layer made from such a sinter-bonding composition. The dicing tape with a sinter-bonding sheet (X) has such a sinter-bonding sheet (10) and a dicing tape (20). The dicing tape (20) has a lamination structure containing a base material (21) and an adhesive layer (22), and the sinter-bonding sheet (10) is positioned on the adhesive layer (22) of the dicing tape (20).

A manufacturing method includes the step of laminating a sheet assembly onto chips arranged on a processing tape, where the sheet assembly has a multilayer structure including a base and a sinter-bonding sheet and is laminated so that the sinter-bonding sheet faces the chips, and subsequently removing the base B from the sinter-bonding sheet. The chips on the processing tape are picked up each with a portion of the sinter-bonding sheet adhering to the chip, to give sinter-bonding material layer-associated chips. The sinter-bonding material layer-associated chips are temporarily secured through the sinter-bonding material layer to a substrate. The sinter-bonding material layers lying between the temporarily secured chips and the substrate are converted through a heating process into sintered layers, to bond the chips to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to semiconductor chips while reducing loses of the sinter-bonding material.

A manufacturing method includes the step of laminating a sheet assembly onto chips arranged on a processing tape, where the sheet assembly has a multilayer structure including a base and a sinter-bonding sheet and is laminated so that the sinter-bonding sheet faces the chips, and subsequently removing the base B from the sinter-bonding sheet. The chips on the processing tape are picked up each with a portion of the sinter-bonding sheet adhering to the chip, to give sinter-bonding material layer-associated chips. The sinter-bonding material layer-associated chips are temporarily secured through the sinter-bonding material layer to a substrate. The sinter-bonding material layers lying between the temporarily secured chips and the substrate are converted through a heating process into sintered layers, to bond the chips to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to semiconductor chips while reducing loses of the sinter-bonding material.

A semiconductor package includes a lower semiconductor chip disposed on a substrate, at least one upper semiconductor chip disposed on the lower semiconductor chip, a heat spreader bonded on the lower semiconductor chip and the at least one upper semiconductor chip, and an encapsulant surrounding side surfaces of the heat spreader. A lower surface of the heat spreader includes a first protrusion and a non-protruding portion, the first protrusion is in contact with an upper surface of the lower semiconductor chip, and the non-protruding portion is in contact with an upper surface of the at least one upper semiconductor chip.

A semiconductor package includes a lower semiconductor chip disposed on a substrate, at least one upper semiconductor chip disposed on the lower semiconductor chip, a heat spreader bonded on the lower semiconductor chip and the at least one upper semiconductor chip, and an encapsulant surrounding side surfaces of the heat spreader. A lower surface of the heat spreader includes a first protrusion and a non-protruding portion, the first protrusion is in contact with an upper surface of the lower semiconductor chip, and the non-protruding portion is in contact with an upper surface of the at least one upper semiconductor chip.

A semiconductor packaging device includes a first patterned insulation layer, a patterned conductive layer, a semiconductor device and an encapsulant. The first patterned insulation layer has a first surface, a second surface opposite the first surface, and an island portion having the first surface. The first patterned insulation layer defines a tapered groove surrounding the island portion. The patterned conductive layer is disposed on the first surface of the island portion. The semiconductor device electrically connects to the patterned conductive layer. The encapsulant encapsulates the semiconductor device, the first patterned insulation layer and the patterned conductive layer.

A semiconductor packaging device includes a first patterned insulation layer, a patterned conductive layer, a semiconductor device and an encapsulant. The first patterned insulation layer has a first surface, a second surface opposite the first surface, and an island portion having the first surface. The first patterned insulation layer defines a tapered groove surrounding the island portion. The patterned conductive layer is disposed on the first surface of the island portion. The semiconductor device electrically connects to the patterned conductive layer. The encapsulant encapsulates the semiconductor device, the first patterned insulation layer and the patterned conductive layer.

A low temperature cofired ceramic substrate comprises a plurality of dielectric layers, at least one inner conductor layer, a plurality of bond pads, and a solder mask. The dielectric layers are formed from ceramic material and placed one on top of another to form a stack. The inner conductor is formed from electrically conductive paste and positioned on an upper surface of at least one inner dielectric layer. The bond pads are positioned on an outer surface of the stack. Each bond pad is formed from a plurality of conductive sublayers of thin film metal stacked one on top of another, with each conductive sublayer being formed from a different metal. The solder mask is positioned on the same outer surface of the stack as the bond pads and includes a plurality of openings, with each opening exposing at least a portion of one of the bond pads.

A semiconductor package device includes a first conductive structure, a second conductive structure and a dielectric layer. The first conductive structure has a tapered portion. The second conductive structure surrounds the tapered portion of the first conductive structure and is in direct contact with a side wall of the tapered portion of the first conductive structure. The dielectric layer surrounds the tapered portion of the first conductive structure and is in direct contact with the side wall of the tapered portion of the first conductive structure.

A semiconductor package device includes a first conductive structure, a second conductive structure and a dielectric layer. The first conductive structure has a tapered portion. The second conductive structure surrounds the tapered portion of the first conductive structure and is in direct contact with a side wall of the tapered portion of the first conductive structure. The dielectric layer surrounds the tapered portion of the first conductive structure and is in direct contact with the side wall of the tapered portion of the first conductive structure.