A feedback circuit of a voltage regulator with adaptive voltage positioning (AVP) includes a first sensing circuit, a second sensing circuit, a third sensing circuit, and a processing circuit. The first sensing circuit generates a first feedback signal that provides information of an inductor current of the voltage regulator. The second sensing circuit generates a second feedback signal that provides information of an output voltage of the voltage regulator. The third sensing circuit generates a third feedback signal that provides information of a capacitor current of an output capacitor of the voltage regulator. The processing circuit generates a control voltage signal according to the first feedback signal, the second feedback signal, and the third feedback signal, and outputs the control voltage signal to a controller circuit of the voltage regulator for regulating the output voltage of the voltage regulator.

A feedback circuit of a voltage regulator with adaptive voltage positioning (AVP) includes a first sensing circuit, a second sensing circuit, a third sensing circuit, and a processing circuit. The first sensing circuit generates a first feedback signal that provides information of an inductor current of the voltage regulator. The second sensing circuit generates a second feedback signal that provides information of an output voltage of the voltage regulator. The third sensing circuit generates a third feedback signal that provides information of a capacitor current of an output capacitor of the voltage regulator. The processing circuit generates a control voltage signal according to the first feedback signal, the second feedback signal, and the third feedback signal, and outputs the control voltage signal to a controller circuit of the voltage regulator for regulating the output voltage of the voltage regulator.

The present invention discloses a method of standby power supply including steps of: detecting a loading level; determining the loading level; entering a select mode; selecting a standby mode; entering a no-load mode, or a sleep mode, or a power-down mode; during the no-load mode, generating a no-load sustaining power, and returning back to detect the loading level when a preset condition is met; during the sleep mode, generating a sleep sustaining power, and returning back to detect the loading level when the preset condition is met; during the power-down mode, ceasing the power and entering a power-down recovery mode; and during the power-down recovery mode, returning back to detect the loading level when the preset condition is met. Therefore, the present invention implements power conversion for normal power supply, and particularly effectively controls the amount of power in the standby state, thereby greatly reducing power consumption and improving power saving.

A supply node receives supply voltage and an output node provides a regulated output voltage to a load. A switching transistor is coupled between the supply and output nodes. The switching transistor is controlled by a drive signal generated by a control circuit to control switching activity. The control circuit includes circuitry to sense a feedback voltage indicative of the regulated output voltage and a comparator generating a comparison logic signal dependent on a comparison of the feedback voltage to a reference. A logic circuit generates a skip signal in response to the comparison logic signal. A counter generates a termination signal. Signal processing circuitry controls the switching activity by asserting the drive signal as a function of the skip signal and the termination signal.

A supply node receives supply voltage and an output node provides a regulated output voltage to a load. A switching transistor is coupled between the supply and output nodes. The switching transistor is controlled by a drive signal generated by a control circuit to control switching activity. The control circuit includes circuitry to sense a feedback voltage indicative of the regulated output voltage and a comparator generating a comparison logic signal dependent on a comparison of the feedback voltage to a reference. A logic circuit generates a skip signal in response to the comparison logic signal. A counter generates a termination signal. Signal processing circuitry controls the switching activity by asserting the drive signal as a function of the skip signal and the termination signal.

A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a diode coupled between the input node and an output node, and an output capacitor coupled between the output node and ground such that an output voltage is formed across the output capacitor. A switch selectively couples the input node to ground in response to a drive signal. Control loop circuitry includes an error amplifier to generate an analog error voltage based upon a comparison of a feedback voltage to a reference voltage, the feedback voltage being indicative of the output voltage, a quantizer to quantize the analog error voltage to produce a digital error signal, and a drive voltage generation circuit to generate the drive signal as having a duty cycle based upon the digital error signal.

A system may include a power converter comprising at least one stage having a dual anti-wound inductor having a first winding and a second winding constructed such that its windings generate opposing magnetic fields in its magnetic core and constructed such that a coupling coefficient between the first winding and the second winding is less than approximately 0.95 and a current control subsystem for controlling an electrical current through the dual anti-wound inductor, the current control subsystem configured to minimize a magnitude of a magnetizing electrical current of the dual anti-wound inductor to prevent core saturation of the dual anti-wound inductor and regulate an amount of output electrical current delivered by the power converter to the load in accordance with a reference input signal.

A direct current (DC) to DC (DC-DC) converter includes a comparator configured to set a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL configured increase the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer configured to selectively output a delayed version of the signal pulse; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit configured to adaptively adjust a precision of the DC-DC converter in accordance with a duty cycle of the DC-DC converter and a setpoint of the DC-DC converter.

An electrical circuit for reducing electromagnetic noise or interference in a power converter. The circuit includes at least one shunt capacitor arranged to connect with a grounded component of the power converter, wherein the at least one shunt capacitor is further arranged to be driven by an active control signal so as to sink a noise current originating from a noise source to the grounded component of the power converter, wherein the noise source is connected to the grounded component via a capacitive path formed by at least one stray capacitors.

An electrical circuit for reducing electromagnetic noise or interference in a power converter. The circuit includes at least one shunt capacitor arranged to connect with a grounded component of the power converter, wherein the at least one shunt capacitor is further arranged to be driven by an active control signal so as to sink a noise current originating from a noise source to the grounded component of the power converter, wherein the noise source is connected to the grounded component via a capacitive path formed by at least one stray capacitors.