A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.

In an example, a system includes a phase-locked loop including a charge pump coupled to a phase frequency detector, a low-pass filter coupled to the charge pump, and a VCO coupled to the low-pass filter, where the charge pump is configured to provide a charge pump current to the low-pass filter. The system also includes a current source configured to provide a bias current to the charge pump. The system includes a first bias compensation circuit configured to increase the bias current responsive to a control voltage provided to the VCO being within a first range. The system also includes a second bias compensation circuit configured to decrease the bias current responsive to the control voltage provided to the VCO being within a second range.

A transceiver may include a reception (Rx) radio frequency (RF) part configured to process a received signal, a transmission (Tx) RF part configured to process a transmitted signal, and a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part. The PLL may be controlled according to whether the reception RF part or the transmission RF part is on. In addition, a transceiver may include quenching waveform generator (QWGs) to control quenching waveforms of the RF parts corresponding to a plurality of antennas. The quenching waveforms may be generated respectively by VCOs operating at a same frequency. The QWGs may control the VCOs such that the quenching waveforms do not overlap.

A circuit receives a reference clock and output an output clock in accordance with a clock multiplication factor, the circuit comprising: a digitally controlled timing adjustment circuit, a timing detection circuit, a loop filter, a controllable oscillator, a clock divider, a modulator, and a calibration circuit, wherein the modulator is configured to modulate a clock multiplication factor into a division factor and also calculate a pre-known noise caused by the modulation, and the digitally controlled timing adjustment circuit, the timing detection circuit, the loop filter, the controllable oscillator, and the clock divider form a feedback loop such that a frequency of the output clock is equal to a frequency of the reference clock multiplied by the clock multiplication, but a pre-known noise caused by the modulation is corrected by the digitally controlled timing adjustment circuit, which is calibrated by the calibration circuit in a closed-loop manner to minimize a correlation between the pre-known noise and an output of the timing detection circuit.

A phase-locked loop device may include the following elements: a phase frequency detector configured to generate a control signal; a charge pump connected to the phase frequency detector; a loop filter connected to the charge pump and configured to generate a control voltage based on a first current received from the charge pump, wherein the charge pump is configured to generate a second current based on the control signal and a first copy of the control voltage and to provide the second current to the loop filter, the second current being linearly related to the control voltage; a voltage-controlled oscillator connected to the loop filter and configured to generate an output signal based on a second copy of the control voltage, wherein a frequency of the output signal is directly proportional to the control voltage; and a signal processor connected between the voltage-controlled oscillator and the phase frequency detector.

The present disclosure discloses a multi-standard performance reconfigurable I/Q orthogonal carrier generator. The generator may implement a continuously covered I/Q carrier output of 0.1-5 GHz and continuously covered differential signal outputs of 5-10 GHz and 1.5-3 GHz by means of reasonable frequency assignment; also, carrier signals under various frequencies with different loop bandwidths, different phase noises, different power consumption levels and different locking times can be generated by configuring a programmable charge pump (102), a loop filter (103) parameter, a multi-path voltage-controlled oscillator (104) and a first multiplexer (105) corresponding thereto, a five-stage-division-by-two frequency division link (109) and a corresponding second multiplexer (110) and third multiplexer (112), so as to implement generation of a multi-standard performance reconfigurable I/Q orthogonal carrier.

A transceiver may include a reception (Rx) radio frequency (RF) part configured to process a received signal, a transmission (Tx) RF part configured to process a transmitted signal, and a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part. The PLL may be controlled according to whether the reception RF part or the transmission RF part is on. In addition, a transceiver may include quenching waveform generator (QWGs) to control quenching waveforms of the RF parts corresponding to a plurality of antennas. The quenching waveforms may be generated respectively by VCOs operating at a same frequency. The QWGs may control the VCOs such that the quenching waveforms do not overlap.

A phase-locked loop device may include the following elements: a phase frequency detector configured to generate a control signal; a charge pump connected to the phase frequency detector; a loop filter connected to the charge pump and configured to generate a control voltage based on a first current received from the charge pump, wherein the charge pump is configured to generate a second current based on the control signal and a first copy of the control voltage and to provide the second current to the loop filter, the second current being linearly related to the control voltage; a voltage-controlled oscillator connected to the loop filter and configured to generate an output signal based on a second copy of the control voltage, wherein a frequency of the output signal is directly proportional to the control voltage; and a signal processor connected between the voltage-controlled oscillator and the phase frequency detector.

A charge pump of a phase-locked loop (PLL) circuit includes a current source circuit, a current sink circuit, and a biasing circuit. The biasing circuit includes a current digital-to-analog converter (IDAC) and a low-pass filter (LPF). The IDAC provides a reference current in response to a current value setting, wherein a first voltage is established due to the reference current. The LPF applies low-pass filtering to the first voltage to generate a filter output as a second voltage, wherein bias voltages of the current source circuit and the current sink circuit are controlled by the second voltage.

A charge pump has a first current digital to analog converter connected to a supply voltage terminal and having a first resistance configurable based on a first digital control code, a first switch connected between the first current digital to analog converter and an output terminal, a second current digital to analog converter connected to a reference voltage terminal and having a second resistance configurable based on a second digital control code, and a second switch connected between the output terminal and the second current digital to analog converter, wherein the first current digital to analog converter sources a first current based on the first resistance responsive to the first switch being closed, and the second current digital to analog converter sinks a second current based on the second resistance responsive to the second switch being closed.