A decoding system for an iterative decoding of a parity check code comprises a first loop circuit adapted to store log-likelihood ratio values corresponding to a plurality of received data symbols in a memory unit; a second loop circuit adapted to compute a difference between a check-to-variable log-likelihood message at a second iteration step, and a check-to-variable log-likelihood message at a first iteration step, when the first iteration step precedes the second iteration step; and an adder unit adapted to update a log-likelihood ratio value stored on the first loop circuit by adding the difference computed in the second loop circuit; wherein the first loop circuit and the second loop circuit are synchronized such that the adder unit forwards the updated log-likelihood ratio value synchronously both to the first loop circuit and to the second loop circuit.

The method for shuffled decoding of LDPC codes includes calculating check-variable mutual information which is mutual information of a message propagating from a plurality of check nodes to a plurality of variable nodes by a check-variable mutual information calculating unit, calculating variable-check mutual information which is mutual information of a message propagating from the plurality of variable nodes to the plurality of check nodes connected to the plurality of variable nodes based on the check-variable mutual information by a variable-check mutual information calculating unit, and Calculating the entire mutual information which is a sum of variable-check mutual information for each of the plurality of variable nodes and determines an operation order of a variable node having the largest entire mutual information among the plurality of variable nodes to be next, by an operation order determining unit.

Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is P.sub.CNB (where PP.sub.CNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than P.sub.CNB*q bits.

Methods and apparatus for decoding LDPC codes provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. In an embodiment, a configurable LDPC decoder, which supports many different LDPC codes having any sub-matrix size, comprises several independently addressable memories which are used to store soft decision data for each bit node. The decoder further comprises a number, P, of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is P.sub.CNB (where PP.sub.CNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than P.sub.CNB*q bits.

An error correction decoding apparatus includes column operators 201 and row operators 211 to 213 provided respectively in accordance with the columns and rows of a check matrix of an LDPC code. A received LLR (log-likelihood ratio) of a received sequence is input into the column operators 201 together with row LLRs from the row operators 211 to 213, whereupon the column operators 201 calculate a total value z.sub.1 of the received LLR of the received sequence and the row LLRs from the row operators 211 to 213. The row operators 211 to 213 hold operation results relating to row LLRs or column LLRs obtained during a previous operation, calculate column LLRs using the total value input from the column operators 201 and the held operation results, calculate row LLRs from the calculated column LLRs, and output the calculated row LLRs to the column operators 201.

Methods and systems are provided for low-power decoding. An example system may include one or more storage circuits and a decoder circuit. The decoder circuit may implement a plurality of nodes for use during decoding, including at least one data generating node and at least one data checking node, and the storage circuits may store status information associated with the nodes, the status information indicating when each corresponding node is locked or unlocked. During decoding operations, the decoder circuit may set the status information to lock one or more of the nodes based on one or more locking conditions, and may cease decoding based on one or more ceasing conditions. The decoder circuit may locks a data generating node when a corresponding calculated value meets a particular condition, and may lock a data checking node when all data generating nodes associated with it are locked.

In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.

Some embodiments are directed to a method for controlling a check node of a NB-LDPC decoder. The check node receives d.sub.c input lists U.sub.i and delivers and delivers d.sub.c output lists V.sub.i, with i[1 . . . d.sub.c]. Each input list and output list includes n.sub.m elements and each element of the input or output lists includes a reliability value associated to a symbol of a Galois Field GF(q) with q>n.sub.m. The input elements and output elements are sorted according to the reliability values in the lists. The method is a syndrome-based method. The syndromes are sums of d.sub.c elements of input lists U.sub.i. The method includes a step of syndrome calculation, a step of decorrelation and a step for generating the output list.

An embodiment of an electronic apparatus comprises one or more substrates, and logic coupled to the one or more substrates, the logic to detect unreliable messages between check nodes and variable nodes in association with an error correction operation, determine respective degrees of unreliability for the unreliable messages, and reduce an influence of the unreliable messages on the error correction operation, as compared to an influence of reliable messages between the check nodes and the variables nodes, based on the determined respective degrees of unreliability. Other embodiments are disclosed and claimed.

This application is directed to compressing check node data for an electronic device. The electronic device identifies a check node corresponding to a subset of codeword symbols in a block of data and determines check node data that indicates a likelihood of the subset of codeword symbols being erroneous. A set of data bits are determined based on a value combination of data items of the check node data to uniquely identify the value combination among a set of selected value combinations according to a predefined relationship. The electronic device stores, in a memory block, the set of data bits representing the data items of the check node data of the check node. Each data item requires more data bits to represent all possible values of the respective data item than data bits of the set of data bits.