Apparatuses, systems, and techniques to decode encoded data for fifth-generation (5G) new radio (NR). In at least one embodiment, a processor includes one or more circuits to select one or more data decoding operations to decode one or more 5G signals based, at least in part, on a sparsity of data received by the processor.

Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.

A device is disclosed. The device may include an input buffer to receive a first low bit width message. A reconstruction circuit may implement a reconstruction function on the first low bit width message, producing a first high bit width message. A computation circuit may implementing a computation function on the first high bit width message, producing a second high bit width message. A quantization circuit may implementing a quantization function on the second high bit width message, producing a second low bit width message. A decision buffer may then store the second low bit width message. The reconstruction function and the quantization function may vary depending on an iteration and a layer of the device.

A method of accessing a memory space of a memory device with a decoder, the memory space having faults, including the steps of performing a memory access operation by an electronic device to a access a logical memory space of the memory device, and randomizing the memory access operation with a randomization logic to access data from a physical memory space based on the logical memory space, the randomization logic providing time varying behavior for accessing the physical memory space.

A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.

An iterative decoder, comprises:

N variable nodes (VNs) v.sub.n, n=1 . . . N, configured to receive a LLR I.sub.n defined on a alphabet A.sub.l of q.sub.ch quantization bits, q.sub.ch≥2;

M constraint nodes (CNs) c.sub.m, m=1 . . . M, 2≤M<N;

v.sub.n and c.sub.m exchanging messages along edges of a Tanner graph;

each v.sub.n sending messages m.sub.v.sub.n.sub..fwdarw.c.sub.m, the set of connected constraint nodes being noted V.sub.(vn), and V.sub.(vn)\{cm} being V.sub.(vn) except c.sub.m, and,

each c.sub.m sending messages m.sub.c.sub.m.sub..fwdarw.v.sub.n to v.sub.n;

the LLR I.sub.n and the messages m.sub.v.sub.n.sub..fwdarw.c.sub.m and m.sub.c.sub.m.sub..fwdarw.v.sub.n are coded; and

each variable node v.sub.n, for each iteration l, compute:

sign-preserving factors:

[00001]$=\xi \times \mathrm{sign}\left(I_n\right)+{.Math.}_{c\in V\left(v_n\right)\backslash \left\{c_m\right\}}\mathrm{sign}\left(\right)$

where ξis a positive or a null integer;

[00002]$=I_n+\frac{1}{2}\times +{.Math.}_{c\in V\left(v_n\right)\backslash \left\{c_m\right\}}\left(\right)$

and

An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.

An LDPC decoding method of a received signal including a plurality of received symbols is provided. A decoding apparatus selects a perturbation space in which perturbation is to be performed based on a code length of the received signal and a maximum number of perturbation rounds indicating a number of perturbation rounds that can be performed, and performs a perturbation round. The decoding apparatus performs perturbation on a corresponding received symbol among the plurality of received symbols in each perturbation round, and decodes the received signal on which the perturbation has been performed. The decoding apparatus determines that decoding is successful when there is a perturbation round in which a decoding result of the received signal satisfies a predetermined condition.

Low-density parity-check (LDPC) encoded data with one or more errors and information associated with an early convergence checkpoint are received. The information associated with the early convergence checkpoint is used to perform LDPC decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword where the early convergence checkpoint is prior to a first complete iteration of the LDPC decoding. It is determined whether the LDPC decoding is successful and in the event it is determined that the LDPC decoding is successful, the decoded codeword is output.

A system for a fiber-optic network includes a transceiver. The transceiver includes a fiber-optic interface unit and a host unit. The host unit includes a low-complexity error correction decoder and a high-complexity error correction decoder. One or both from the low-complexity error correction decoder and the high-complexity error correction decoder are selected to decode input data from the fiber-optic interface unit, the input data including codewords.