Read data associated with Flash storage is received. One of a plurality of LLR mapping tables is selected and a set of one or more LLR values is generated using the read data and the selected LLR mapping table, where each LLR value in the set of LLR values has a same finite precision as a finite-precision low-density parity-check (LDPC) decoder. Error-corrected read data is generated using the set of LLR values, where the finite-precision LDPC decoder has the same finite precision as the set of LLR values. The error-corrected read data is output.

A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.

Systems, apparatuses and methods may provide for technology to receive a codeword containing an SC-LDPC code and conduct a min-sum decode of the SC-LDPC code based on a plurality of scaling factors. In an embodiment, the scaling factors are non-uniform across check nodes and multiple iterations of the min-sum decode.

Embodiments of the invention provide a check node processing unit configured to determine at least one check node message to decode a signal encoded using a NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units to determine permuted variable node messages by applying permutations to at least three variable node messages generated by variable node processing units; a syndrome calculation unit to determine a set of syndromes comprising binary values from the permuted variable node messages; a decorrelation and permutation unit configured, for each check node message of a given index, to: determine a permuted index by applying the inverse of the one or more permutations; select at least one valid syndrome in the set of syndromes; and determine at least one candidate check node component; and a selection unit to determine at least one check node message from the candidate check node component.

A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

A check node processing unit configured to determine check node messages to decode a signal encoded using NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units configured to determine permuted variable node messages by permuting variable node messages generated by one or more variable node processing units; a syndrome sub-check node configured to determine check node messages from a set of syndromes, the set of syndromes being determined from one or more intermediate messages computed from the permuted variable node messages; a forward-backward sub-check node configured to determine permuted check node messages from the intermediate messages; a switching unit configured to generate check node messages of given index from the check node messages or from the permuted check node messages depending on the giving index.

Memory controllers, decoders and methods to perform decoding of user bits and parity bits including those corresponding to low degree variable nodes. For each of the user bits, the decoder performs a variable node update operation and a check node update operation for connected check nodes. After all of the user bits are processed, the decoder performs a parity node update operation for the parity bits using results of the variable node and check node update operations performed on the user bits.

A low-density parity-check (LDPC) decoder has a check node storage (CNS) architecture to reduce the gate count for the decoder implementation, resulting in a lower footprint relative to traditional designs. The CNS architecture allows a controller to selectively, dynamically swap check nodes of the LDPC decoder between latching circuitry and a volatile memory. The controller can to store active check nodes in the latching circuitry and check nodes not active for a computation in the volatile memory.

A saturation metric that represents a degree of saturation in a low-density parity-check (LDPC) decoding system that uses a fixed-point number representation is determined. The saturation metric is compared against a saturation threshold. In the event the saturation metric exceeds the saturation threshold, at the end of a decoding iteration, a message is more aggressively attenuated compared to when the saturation metric does not exceed the saturation threshold in order to produce an attenuated message. In the event the saturation metric does not exceed the saturation threshold, at the end of the decoding iteration, the message is less aggressively attenuated compared to when the saturation metric does exceed the saturation threshold in order to produce the attenuated message.

An LDPC decoding method of a received signal including a plurality of received symbols is provided. A decoding apparatus selects a perturbation space in which perturbation is to be performed based on a code length of the received signal and a maximum number of perturbation rounds indicating a number of perturbation rounds that can be performed, and performs a perturbation round. The decoding apparatus performs perturbation on a corresponding received symbol among the plurality of received symbols in each perturbation round, and decodes the received signal on which the perturbation has been performed. The decoding apparatus determines that decoding is successful when there is a perturbation round in which a decoding result of the received signal satisfies a predetermined condition.